High resolution FPGA DPWM based on variable clock phase shifting

Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. A. de Castro, "High resolution FPGA DPWM based on variable clock phase shifting" IEEE Transactions on Power Electronics – Letters section, vol.25, no.5, pp.1115 - 1119, mayo 2010This paper proposes a very high resolution DPWM architecture that takes advantage of an FPGA advanced clock management capability: the fine phase shifting of the clock. This feature is available in almost every FPGA nowadays, allowing very small and programmable delays between the input and output clocks. An original use of this fine phaseshifting pushes the limits of DPWM resolution. The experimental results show a time resolution of 19.5 ps in a Virtex-5 FPGA

Estimación estadística de consumo en FPGAs

Tesis doctoral inédita. Universidad Autónoma de Madrid, Escuela Politécnica Superior, junio de 200

Impact of the hardened floating-point cores on HIL technology

The Hardware-In-the-Loop (HIL) technique is increasingly used for testing power electronics. FPGAs (Field-Programmable Gate Array) are becoming usual in this kind of emulation due to their acceleration capabilities. But even using FPGAs, it has not been possible to reach real time simulations when small integration steps are necessary (around 100 ns or lower) if floating-point representation is used. Fixed-point has been the solution, but at a high design effort cost. With the release of FPGAs with HFP (Hardened Floating-Point) cores – dedicated floating-point blocks implemented in silicon – the minimum achievable simulation step decreases significantly. This paper presents a comparison between HFP cores, floating-point in programmable logic and fixed-point for HIL models. Results show that both HFP-based and fixed-point arithmetic achieve a simulation step around 10 ns for a full-bridge converter model. A comparison regarding resolution and accuracy is also presented, because acceleration is not the only issue when decreasing the integration step. Numerical resolution also plays an important role, and 32-bit floating-point representation finds a double barrier: acceleration marked by technology, and numerical resolution. Both are explored in this paperThis work has been supported by the Spanish Ministerio deEconomía y Competitividad under project TEC2013-43017-

Estimación de Capacidad en FPGAs Comerciales

La estimación de consumo medio en circuitos CMOS es un problema aun no resuelto completamente debido a la dificultad en la estimación de la actividad de conmutación. Cuando se trabaja con FPGAs comerciales, a este problema se añade la falta de información sobre las capacidades físicas de los nodos del circuito, que se necesita también para estimar el consumo de potencia. En este trabajo se presenta una técnica general para estimar la capacidad de los nodos en un diseño implementado en una FPGA comercial basada en la relación entre capacidad, retardo medio y fan out del nodo. Los resultados preliminares indican que esta solución para estimar capacidades físicas es aplicable con un error tolerable.Eje: FPGARed de Universidades con Carreras en Informática (RedUNCI

Estimación de Capacidad en FPGAs Comerciales

La estimación de consumo medio en circuitos CMOS es un problema aun no resuelto completamente debido a la dificultad en la estimación de la actividad de conmutación. Cuando se trabaja con FPGAs comerciales, a este problema se añade la falta de información sobre las capacidades físicas de los nodos del circuito, que se necesita también para estimar el consumo de potencia. En este trabajo se presenta una técnica general para estimar la capacidad de los nodos en un diseño implementado en una FPGA comercial basada en la relación entre capacidad, retardo medio y fan out del nodo. Los resultados preliminares indican que esta solución para estimar capacidades físicas es aplicable con un error tolerable.Eje: FPGARed de Universidades con Carreras en Informática (RedUNCI

Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course

Due to significant technological advances andindustry requirements, many universities have introduced programmable logic and hardware description languages into undergraduate engineering curricula. This has led to a number of logistical and didactical challenges, in particular for computer science students. In this paper, the integration of some programmable logic concepts into an introductory digital electronics course is presented. The proposed optional lab develops a printed circuit board that implements a programmable logic block. Another contribution is the collaborative problem-solving methodology used to achieve this goal. Surveys completed by the students, and their final grades, show that the lab has improved the quality of their education and has contributed to a successful integration of programmable logic concepts in an introductory digital electronics course. Because of its demands on students? time and effort, the lab favors the most motivated students. This suggests future research on a proposal for a lab that would be feasible within the time constraints for even the least motivated students.Fil: Todorovich, Elías. Universidad Nacional del Centro de la Provincia de Buenos Aires. Facultad de Ciencias Exactas. Instituto de Investigaciones en Tecnología Informática Avanzada; Argentina. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Tandil; ArgentinaFil: Marone, José Antonio. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Tandil; Argentina. Universidad Nacional del Centro de la Provincia de Buenos Aires. Facultad de Ciencias Exactas. Instituto de Investigaciones en Tecnología Informática Avanzada; ArgentinaFil: Vazquez, Martin Osvaldo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Tandil; Argentina. Universidad Nacional del Centro de la Provincia de Buenos Aires. Facultad de Ciencias Exactas. Instituto de Investigaciones en Tecnología Informática Avanzada; Argentin

Resolution analysis of switching converter models for hardware-in-the-loop

Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. O. Goñi, A. Sánchez, E. Todorovich, Á. de Castro, "Resolution Analysis of Switching Converter Models for Hardware-in-the-Loop", IEEE Transactions on Industrial Informatics, vol. 10, no.2, pp.1162 - 1170, May, 2014This work proposes two methods to determine the resolution of state variables in models of switching-mode power converters. The target models are intended for hardware-in-the-loop, i.e., closed-loop emulation using a model of the power converter implemented in digital hardware with the controller in its final implementation. The focus here is on the resolution of fixed-point models, although the results can also be applied to the significand resolution in floating-point representation. The first method is based on the simulation, provides the designer with the optimum resolution values, and guarantees that using the resolution, the converter will behave as it was specified. The second method is fast but conservative, intended for applications without hard constraints of area and speed. Despite the simplicity of the second method, its results, although slightly overestimated, have been demonstrated to be correct by the results of the first method. A boost converter for the power factor correction is used as an application example. As the converter model is intended for field-programmable gate array implementation, its area and maximum clock frequency are also analyzed. In this application example, the results show that the area grows linearly with the number of bits of each state variable, and the clock frequency is dominated by the width of one of the variables.This work was partially supported by the Agencia Nacional de Promoción Científica y Tecnológica, Argentina, through Project PICT 2009 - 0041

OBD-II vehicle data capture and monitoring system prototype

In this work, a prototype of a system for capturing vehicle parameters according to OBD-II technology was designed and built. The prototype is able to read different magnitudes generated by a car through an ELM-327 USB interface that allows communication with the vehicle on-board computer, and the data obtained through a USB GPS. A 3G modem and a USB Wifi adapter were added to the developed prototype. The system was implemented on a Raspberry Pi B platform with the Raspbian operating system. The 3G modem was used to transmit information collected over the Internet to a remote device or exchange. The USB WiFi adapter allowed the Raspberry Pi to be configured as an Access Point. In this way, it could be connected to a mobile device that supports the Android operating system to visualize the data read. The tests were conducted on a Chevrolet Corsa Wagon Life Gls 1.4 4p model 2009.XIII Workshop Arquitectura, Redes (WARSO)Red de Universidades con Carreras en Informática (RedUNCI

Low-power FSMs in FPGA: Encoding alternatives

The final publication is available at Springer via http://dx.doi.org/10.1007/3-540-45716-X_36Proceedings of 12th International Workshop, PATMOS 2002 Seville, Spain, September 11–13, 2002In this paper, the problem of state encoding of FPGA-based synchronous finite state machines (FSMs) for low-power is addressed. Four codification schemes have been studied: First, the usual binary encoding and the One-Hot approach suggested by the FPGA vendor; then, a code that minimizes the output logic; finally, the so-called Two-Hot code strategy. FSMs of the MCNC and PREP benchmark suites have been analyzed. Main results show that binary state encoding fit well with small machines (up to 8 states), meanwhile One-Hot is better for large FSMs (over 16 states). A power saving of up to the 57% can be achieved selecting the appropriate encoding. An areapower correlation has been observed in spite of the circuit or encoding scheme. Thus, FSMs that make use of fewer resources are good candidates to consume less power.Ministry of Science of Spain, under Contract TIC2001-2688-C03-03, has supported this work. Additional funds have been obtained from Projects 658001 and 658004 of the Fundación General de la Universidad Autónoma de Madrid

Prototipo de sistema de captura y monitoreo de datos OBD-II de vehículos

En este trabajo se diseñó y construyó un prototipo de un sistema de captura de parámetros de vehículos según tecnología OBDII. El prototipo es capaz de leer distintas magnitudes generadas por un automóvil a través de una interfaz ELM-327 USB que permite la comunicación con la computadora de a bordo del vehículo en conjunto con los datos obtenidos mediante un GPS USB. Al prototipo desarrollado se le añadió un módem 3G y un adaptador Wifi USB. El sistema se implementó en una plataforma Raspberry Pi B con sistema operativo Raspbian. El módem 3G se utilizó para permitir el envío de la información recolectada a través de Internet a un equipo o central remota, y el adaptador WiFi USB permitió configurar el Raspberry Pi para poder ser utilizado como un Access Point de manera que fuese posible conectarse con un dispositivo móvil que soporte el sistema operativo Android para visualizar los datos leídos. Las pruebas fueron realizadas sobre un automóvil Chevrolet Corsa Wagon Life Gls 1.4 4p modelo 2009.XIV Workshop Bases de Datos y Minería de Datos (WBDDM).Red de Universidades con Carreras en Informática (RedUNCI