Performance Measurement of Smart Services in Mechanical Engineering

The past decades have seen a strategic change of mechanical engineering companies defined as digital servitization. The results are innovative customer-oriented smart service business models that complement the product portfolio. Developing and integrating innovative smart service business models is complex and implies different adjustments that companies at times have difficulties with. Research has reacted to this by providing guidance. Especially in the early stages of the smart service business model development, numerous contributions can be found. However, there seems to be a lack of research when it comes to the market entry of smart services and, in particular, how the performance of named services can be measured. This research-in-progress contributes to the research gap by addressing the question of which indicators are currently applied in big German mechanical engineering companies to measure the market performance of their smart services

Agile acceleration of stateful hash-based signatures in hardware

With the development of large-scale quantum computers, the current landscape of asymmetric cryptographic algorithms will change dramatically. Today’s standards like RSA, DSA, and ElGamal will no longer provide sufficient security against quantum attackers and need to be replaced with novel algorithms. In the face of these developments, NIST has already started a standardization process for new Key Encapsulation Mechanisms (KEMs) and Digital Signatures (DSs). Moreover, NIST has recommended the two stateful Hash-Based Signatures (HBSs) schemes XMSS and LMS for use in devices with a long expected lifetime and limited capabilities for maintenance. Both schemes are also standardized by the IETF. In this work, we present the first agile hardware implementation that supports both LMS and XMSS. Our design can instantiate either LMS, XMSS, or both schemes using a simple configuration setting. Leveraging the vast similarities of the two schemes, the hardware utilization of the agile design increases by 20% in LUTs and only 3% in Flip Flops (FFs) over a standalone XMSS implementation. Furthermore, our approach can easily be configured with an arbitrary number of hash cores and accelerators for the one-time signatures for different application scenarios. We evaluate our implementation on the Xilinx Artix-7 FPGA platform, which is the recommended target for PQC implementations by NIST. We explore potential tradeoffs in the design space and compare our results to previous work in this field