Interactive Consistency Algorithms Based on Voting and Error-Correding Codes

This paper presents a new class of synchronous deterministic non authenticated algorithms for reaching interactive consistency (Byzantine agreement). The algorithms are based on voting and error correcting codes and require considerably less data communication than the original algorithm, whereas the number of rounds and the number of modules meet the minimum bounds. These algorithms based on voting and coding are defined and proved on the basis of a class of algorithms, called the dispersed joined communication algorithm

The synthesis of a hardware scheduler for Non-Manifest Loops

This paper addresses the hardware implementation of a dynamic scheduler for non-manifest data dependent periodic loops. Static scheduling techniques which are known to give near optimal scheduling-solutions for manifest loops, fail at scheduling non-manifest loops, since they lack the run time information needed which makes a static schedule feasible. In this paper a dynamic scheduling approach was chosen to circumvent this problem. We present a case study using VHDL where the focus lies on implementations with minimal memory usage and low communication overhead between various components of the architecture. This has resulted in an efficient and synthesisable system

Design citeria for applications with non-manifest loops

In the design process of high-throughput applications, design choices concerning the type of processor architecture and appropriate scheduling mechanism, have to be made. Take a reed-solomon decoder as an example, the amount of clock cycles consumed in decoding a code is dependent on the amount of errors within that code. Since this is not known in advance, and the environment in which the code is transmitted can cause a variable amount of errors within that code, a processor architecture which employs a static scheduling scheme, has to assume the worst case amount of clock cycles in order to cope with the worst case situation and provide correct results. On the other hand a processor that employs a dynamic scheduling scheme, can gain wasted clock cycles, by scheduling the exact amount of clock cycles that are needed and not the amount of clock cycles needed for the worst case situation. Since processor architectures that employ dynamic scheduling schemes have more overhead, designers have to make their choice beforehand. In this paper we address the problem of making the correct choice of whether to use a static or dynamic scheduling scheme. The strategy is to determine whether the application possess non-manifest behavior\ud and weigh out this dynamic behavior against static scheduling solutions which were quite common in the past. We provide criteria for choosing the correct scheduling architecture for a high throughput application based upon the environmental and algorithm-specification constraints. Keywords¿ Non-manifest loop scheduling, variable latency functional units, dynamic hardware scheduling, self\ud scheduling hardware units, optimized data-flow machine architecture

Mapping Applications to an FPFA Tile

This paper introduces a transformational design method which can be used to map code written in a high level source language, like C, to a coarse grain reconfigurable architecture. The source code is first translated into a control data flow graph (CDFG), which is minimized using a set of behaviour preserving transformations, such as dependency analysis, common subexpression elimination, etc. After applying graph clustering, scheduling and allocation transformations on this minimized graph, it can be mapped onto the target architecture

Interactive Consistency Algorithms Based on Authentication and Error-correcting Codes

In this paper, a class of interactive consistency algorithms is described, based on authentication and error-correcting codes. These algorithms require considerably less data communication than existing algorithms, whereas the required number of modules and communication rounds meet the minimum bounds. The algorithms based on authentication and error-correcting codes are defined and proved on basis of a class of algorithms called the Authenticated Dispersed Joined Communication Algorithms

SIL Transformations on Sequence Edges

Introduction In this note a number of transformations on SIL graphs is described. Most emphasis will be on the transformations in which sequence edges play a crucial role. For a better understanding of the transformations and in order to be able to prove the correctness of the transformations, some attention will be given to the formal semantical model of SIL which is currently being developed. Notice however that the formal semantical model of SIL is still in its pre-development stage and only part of the available information is used. The informal semantics of SIL are explained in #Klo-91#. This note is set up in the following way. First we will explain the formal semantical model with emphasis on modelling behaviour and order, as far this is necessary for proving the transformations. The semantical components which constitute a SIL-graph are de#ned together with the composition rules. Thereafter the division of a SIL-graph in transformation blocks is explained. These trans

Interactive Consistency in Quasi-Asynchronous Systems

In order to make a dependable distributed computer system resilient to arbitrary failures of its processors, deterministic interactive consistency algorithms (ICAs) are required. Thus far, in order to guarantee interactive consistency, all ICAs found in the literature require that all correct processors in the system start the algorithm simultaneously. In a distributed system, it is hard to satisfy this requirement. Therefore, in this paper, we describe a new class of self-synchronizing ICAs that guarantee interactive consistency without the above-mentioned requirement