Analysis and design optimization of enhanced swing CMOS LC oscillators based on a phasor based approach

Analysis and design optimization of enhanced swing, low power CMOS LC oscillators is presented. A phasor analysis based approach for determining the amplitude and phase noise of these oscillators is used. MOSFET operation in cut-off, linear and saturation regions is included. The calculated steady state output amplitude and phase noise from this analysis are in good agreement with Cadence Spectre simulations for different bias conditions. Application of this analysis to the design optimization of LC oscillators is demonstrated.Keywords: ISF, Phasor model, PPV, Spectrum conversion, Design oriented analysis, Voltage biased, Enhanced swing oscillator, Oscillator design, Amplitude analysis, X-coupled, Phase noise, Colpitts oscillator, LC oscillator, Design optimizatio

350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS

A new enhanced swing class-D VCO which operates from a supply voltage as low as 300 mV is presented. The architectural advantages are described along with an analysis for the oscillation frequency. Prototype differential and quadrature variants of the proposed VCO have been implemented in a 65 nm RF CMOS process with a 5 GHz VCO oscillation frequency. At a 350 mV supply, the measured phase noise performance for the quadrature VCO with a 5% tuning range is -137.1 dBc/Hz at 3 MHz offset with a power dissipation of 2.1 mW from a 0.35 V supply. The highest resulting figure-of-merit (FoM) is 198.3 dBc/Hz.©2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works

An Efficient and Accurate Method of Estimating Substrate Noise Coupling in Heavily Doped Substrates

Abstract approved

Design Issues of the Parallel Delta-Sigma A/D Converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of L th -order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M . A parallel delta-sigma A/D converter implementation composed of 2, 4, and 8 second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to non-ideal circuit behavior character..