Compact Implementations of BLAKE-32 and BLAKE-64 on FPGA

We propose compact architectures of the SHA-$3$ candidates BLAKE-32 and BLAKE-64 for several FPGA families. We harness the intrinsic parallelism of the algorithm to interleave the computation of four instances of the $G_i$ function. This approach allows us to design an Arithmetic and Logic Unit with four pipeline stages and to achieve high clock frequencies. With careful scheduling, we completely avoid pipeline bubbles. For the time being, the designs presented in this work are the most compact ones for any of the SHA-3 candidates. We show for instance that a fully autonomous implementation of BLAKE-32 on a Xilinx Virtex-5 device requires 56 slices and two memory blocks

A Compact FPGA Implementation of the SHA-3 Candidate ECHO

We propose a compact architecture of the SHA-3 candidate ECHO for the Virtex-5 FPGA family. Our architecture is built around a 8-bit datapath. We show that a careful organization of the chaining variable and the message block in the register file allows one to design a compact control unit based on a 4-bit counter, an 8-bit counter, and a simple Finite State Machine. A fully autonomous implementation of ECHO on a Xilinx Virtex-5 FPGA requires $127$ slices and a single memory block to store the internal state, and achieves a throughput of $72$Mbps

A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function ECHO

We propose a compact coprocessor for the AES (encryption, decryption, and key expansion) and the cryptographic hash function ECHO on Virtex-$5$ and Virtex-$6$ FPGAs. Our architecture is built around a $8$-bit datapath. The Arithmetic and Logic Unit performs a single instruction that allows for implementing AES encryption, AES decryption, AES key expansion, and ECHO at all levels of security. Thanks to a careful organization of AES and ECHO internal states in the register file, we manage to generate all read and write addresses by means of a modulo-$16$ counter and a modulo-$256$ counter. A fully autonomous implementation of ECHO and AES on a Virtex-$5$ FPGA requires $193$ slices and a single $36$k memory block, and achieves competitive throughputs. Assuming that the security guarantees of ECHO are at least as good as the ones of the SHA-$3$ finalists BLAKE and Keccak, our results show that ECHO is a better candidate for low-area cryptographic coprocessors. Furthermore, the design strategy described in this work can be applied to combine the AES and the SHA-$3$ finalist {G}røstl

A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function Grøstl

This article describes the design of an 8-bit coprocessor for the AES (encryption, decryption, and key expansion) and the cryptographic hash function Grøstl on several Xilinx FPGAs. Our Arithmetic and Logic Unit performs a single instruction that allows for implementing AES encryption, AES decryption, AES key expansion, and Grøstl at all levels of security. Thanks to a careful organization of AES and Grøstl internal states in the register file, we manage to generate all read and write addresses by means of a modulo-128 counter and a modulo-256 counter. A fully autonomous implementation of Grøstl and AES on a Virtex-6 FPGA requires 169 slices and a single 36k memory block, and achieves a competitive throughput. Assuming that the security guarantees of Grøstl are at least as good as the ones of the other SHA-3 finalists, our results show that Grøstl is the best candidate for low-area cryptographic coprocessors

Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and Skein on FPGA

The cryptographic hash functions BLAKE and Skein are built from the ChaCha stream cipher and the tweakable Threefish block cipher, respectively. Interestingly enough, they are based on the same arithmetic operations, and the same design philosophy allows one to design lightweight coprocessors for hashing and encryption. The key element of our approach is to take advantage of the parallelism of the algorithms to deeply pipeline our Arithmetic an Logic Units, and to avoid data dependencies by interleaving independent tasks. We show for instance that a fully autonomous implementation of BLAKE and ChaCha on a Xilinx Virtex-6 device occupies 144 slices and three memory blocks, and achieves competitive throughputs. In order to offer the same features, a coprocessor implementing Skein and Threefish requires a substantial higher slice count

Effect of an Oral Adsorbent, AST-120, on Dialysis Initiation and Survival in Patients with Chronic Kidney Disease

The oral adsorbent AST-120 has the potential to delay dialysis initiation and improve survival of patients on dialysis. We evaluated the effect of AST-120 on dialysis initiation and its potential to improve survival in patients with chronic kidney disease. The present retrospective pair-matched study included 560 patients, grouped according to whether or not they received AST-120 before dialysis (AST-120 and non-AST-120 groups). The cumulative dialysis initiation free rate and survival rate were compared by the Kaplan-Meier method. Multivariate analysis was used to determine the impact of AST-120 on dialysis initiation. Our results showed significant differences in the 12- and 24-month dialysis initiation free rate (P < 0.001), although no significant difference was observed in the survival rate between the two groups. In conclusion, AST-120 delays dialysis initiation in chronic kidney disease (CKD) patients but has no effect on survival. AST-120 is an effective therapy for delaying the progression of CKD

Efficacy of SMART Stent Placement for Salvage Angioplasty in Hemodialysis Patients with Recurrent Vascular Access Stenosis

Vascular access stenosis is a major complication in hemodialysis patients. We prospectively observed 50 patients in whom 50 nitinol shape-memory alloy-recoverable technology (SMART) stents were used as salvage therapy for recurrent peripheral venous stenosis. Twenty-five stents each were deployed in native arteriovenous fistula (AVF) and synthetic arteriovenous polyurethane graft (AVG) cases. Vascular access patency rates were calculated by Kaplan-Meier analysis. The primary patency rates in AVF versus AVG at 3, 6, and 12 months were 80.3% versus 75.6%, 64.9% versus 28.3%, and 32.3% versus 18.9%, respectively. The secondary patency rates in AVF versus AVG at 3, 6, and 12 months were 88.5% versus 75.5%, 82.6% versus 61.8%, and 74.4% versus 61.8%, respectively. Although there were no statistically significant difference in patency between AVF and AVG, AVG showed poor tendency in primary and secondary patency. The usefulness of SMART stents was limited in a short period of time in hemodialysis patients with recurrent vascular access stenosis

Skin Perfusion Pressure Is a Prognostic Factor in Hemodialysis Patients

Peripheral arterial disease (PAD) is common in hemodialysis patients and predicts a poor prognosis. We conducted a prospective cohort study to identify risk factors for PAD including skin perfusion pressure (SPP) in hemodialysis patients. The cohort included 373 hemodialysis patients among 548 patients who received hemodialysis at Oyokyo Kidney Research Institute, Hirosaki, Japan from August 2008 to December 2010. The endpoints were lower limb survival (peripheral angioplasty or amputation events) and overall survival of 2 years. Our results showed that <70 mmHg SPP was a poor prognosis for the lower limb survival and overall survival. We also identified age, history of cardiovascular disease, presence of diabetes mellitus, smoking history, and SPP < 70 mmHg as independent risk factors for lower limb survival and overall survival. Then, we constructed risk criteria using the significantly independent risk factors. We can clearly stratify lower limb survival and overall survival of the hemodialysis patients into 3 groups. Although the observation period is short, we conclude that SPP value has the potential to be a risk factor that predicts both lower limb survival and the prognosis of hemodialysis patients