Reconfigurable Intelligent Optical BackPlane for Parallel Computing and Communications

A reconfigurable intelligent optical backplane architecture for parallel computing and communications is described. The backplane consists of a large number of reconfigurable optical channels organized in a ring with relatively simple point-to-point optical interconnections between neighboring smart-pixel arrays. The intelligent backplane can implement (l) dynamically reconfigurable connections between any printed circuit boards, (2) dynamic embeddings of classical interconnection networks such as buses, rings, multidimensional meshes, hypercubes, shuffles, and crossbars, (3) multipoint switching, (4) sorting, (5) parallel-prefix operations, (6) pattern-matching operations, (7) snoopy caches and intelligent memory systems, and (8) media-access control functions. The smart-pixel arrays can be enhanced to include more complex functions, such as queuing and routing, as the technologies mature. Descriptions of the architecture and the smart-pixel arrays and discussions of the system cost, availability, and performance are included

Architecture of a Terabit Free-Space Intelligent Optical Backplane

Optical technologies can support thousands of high bandwidth optical channels to/from a single CMOS integrated circuit, and can thus allow for the construction of novel bandwidth-intensive computing architectures which are no longer constrained by conventional electronic wiring limitations. In this paper, the architecture of a dynamically reconfigurableIntelligent Optical Backplaneis described. The backplane consists of a large number of parallel optical channels (typically 1000–10,000 bits) spaced a few hundred micrometers apart. The optical channels are arranged into upstream and downstream rings, where the channel access protocols are implemented by “smart pixel arrays.” The architecture exploits thebandwith advantageof the optical domain and can be dynamically reconfigured to embed conventional interconnection networks, including multiple busses, rings, and meshes. Unlike all-optical and passive optical systems, the proposed backplane is intelligent and can support communication primitives used in shared memory multiprocessing, including broadcasting, multicasting, acknowledgment, flow and error-control, buffering, shared memory caching, and synchronization. The backplane is also manufacturable using existing optoelectronic technologies. A second generation backplane supporting a distributed shared memory multi-processor is under development

Field-Programmable Smart-Pixel Arrays: Design, VLSI Implementation, and Applications

A smart-pixel array is a two-dimensional array of optoelectronic devices that combine optical inputs and outputs with electronic processing circuitry. A field-programmable smart-pixel array (FP-SPA) is a smart-pixel array capable of having its electronic functionality dynamically programmed in the field. Such devices could be used in a diverse range of applications, including optical switching, optical digital signal processing, and optical image processing. We describe the design, VLSI implementation, and applications of a first-generation FP-SPA implemented with the 0.8-μm complementary metal-oxide semiconductor–self-electro-optic effect device technology made available through the Lucent Technologies–Advanced Research Projects Agency Cooperative (Lucent/ARPA/COOP) program. We report spice simulations and experimental results of two sample applications: In the first application, we configure this FP-SPA as an array of free-space optical binary switches that can be used in optical multistage networks. In the second, we configure the device as an optoelectronic transceiver for a dynamically reconfigurable free-space intelligent optical backplane called the hyperplane. We also describe the testing setup and the electrical and the optical tests that demonstrate the correct functionality of the fabricated device. Such devices have the potential to reduce significantly the need for custom design and fabrication of application-specific optoelectronic devices in the same manner that field-programmable gate arrays have largely eliminated the need for custom design and fabrication of application-specific gate arrays, except in the most demanding applications

Terabit optical local area networks for multiprocessing systems

The design of a scalable optical local area network for multiprocessing systems is described. Each workstation has a parallel-fiber-ribbon optical link to a centralized complementary metal-oxide silicon ͑CMOS͒ switch core, implemented on a single compact printed circuit board ͑PCB͒. When the Motorola Optobus fiber technology is used, each workstation has a data bandwidth of 6.4 Gbits͞s to the core. A centralized switch core interconnecting 32 workstations supports a 204-Gbit͞s aggregate data bandwidth. The switch core is based on a conventional broadcast-and-select architecture, implemented with parallel CMOS integrated circuits ͑IC's͒. The switch core scales well; by incorporation of the CMOS optoelectronic IC's with optical input-output, the electrical core can be reduced to a single-chip optoelectronic IC with terabit capacities. A prototype of an optoelectronic switch core has been fabricated and is described. The appeal of the architecture includes its reliance on commercially available parallelfiber technology, its reliance on the well-developed markets of local area networks and networks of workstations, and its smooth scalability from the electrical to optical domains as technology matures

A Hybrid-SEED Smart Pixel Array for a Four-Stage Intelligent Optical Backplane Demonstrator

This paper describes the VLSI design, layout, and testing of a Hybrid-SEED smart pixel array for a four-stage intelligent optical backplane. The Hybrid-SEED technology uses CMOS silicon circuitry with GaAs-AlGaAs multiple-quantum-well modulators and detectors. The chip has been designed based on the HyperPlane architecture and is composed of four smart pixels which act as a logical 4-bit parallel optical channel. It has the ability to recognize a 4-bit address header, inject electrical data onto the backplane, retransmit optical data, and extract optical data from the backplane. In addition, the smart pixel array can accommodate for optical inversions and bit permutations by appropriate selections of multiplexers. Initial data pertaining to the electrical performance of the chip will be provided and a complete logical description will be given