Mission-based reliability prediction in component-based systems

This paper develops a framework for the extraction of a reliability block diagram in component-based systems for reliability prediction with respect to specific missions. A mission is defined as a composition of several high-level functions occurring at different stages and for a specific time during the mission. The high-level functions are decomposed into lower-level functions, which are then mapped to their corresponding components or component assemblies. The reliability block diagram is obtained using functional decomposition and function-component association. Using the reliability block diagram and the reliability information on the components such as failure rates, the reliability of the system carrying out a mission can be estimated. The reliability block diagram is evaluated by converting it into a logic (Boolean) expression. A modeling language created using the Generic Modeling Environment (GME) platform is used, which enables modeling of a system and captures the functional decomposition and function-component association in the system. This framework also allows for real-time monitoring of the system performance where the reliability of the mission can be computed over time as the mission progresses. The uncertainties in the failure rates and operational time of each high-level function are also considered which are quantified through probability distributions using the Bayesian framework. The dependence between failures of components are also considered and are quantified through a Bayesian network (BN). Other quantities of interest such as mission feasibility and function availability can also be assessed using this framework. Mission feasibility analysis determines if the mission can be accomplished given the current state of components in the system, and function availability provides information whether the function will be available in the future given the current state of the system. The proposed methodology is demonstrated using a radio-controlled (RC) car to carry out a simple surveillance mission

Embedded System Validation for Polymorphous Computing Architectures

Performance verification is a key capability in the successful design, construction, and fielding of realtime embedded systems. Current system design technology has very limited capability for verifying systems from designs and simulations. While formal verification and simulation should be employed as possible, validation (and especially continuous, ‘in-vivo ’ validation) is critical to fielding of reliable systems. Verification of systems typically involves a structured testing process. The system is instrumented and exposed to simulated external events. The instrumentation records the system’s response, and these responses are compared to design parameters and system specifications. The instrumentation can take several forms: 1. Hardware instrumentation is typically the least performance-intrusive method. Examples of hardware instrumentation are: • Logic Analyzers or Emulators: These monitor a processor and its busses to gain a detailed view of the processor’s execution. Instruction sequences and detailed traces can be initiated from userprogrammed triggers. A highly accurate time-base permits the tester to know the exact internal details of the system under test. The drawback of this approach is expense. It requires hardwar

Hardware/Software Runtime Environment for Dynamically Reconfigurable Systems

Dynamically reconfigurable architecture computational devices offer a promise of high speed, low cost, and small form-factor by (1) optimizing the architecture for the application, (2) adapting to changing requirements by reallocating hardware, and (3) using low-cost commodity components. These benefits, however, can be lost if the cost of implementing an efficient system is too high, and the ability to migrate to new technology is unsupported. A set of design and implementation tools, including a run-time architecture is required to meet these goals. The design tools must support high-level specification and synthesis of reconfigurable systems. The run-time environment must serve as a targe