Clock and Trigger Synchronization between Several Chassis of Digital Data Acquisition Modules

In applications with segmented high purity Ge detectors or other detector arrays with tens or hundreds of channels, where the high development cost and limited flexibility of application specific integrated circuits outweigh their benefits of low power and small size, the readout electronics typically consist of multi-channel data acquisition modules in a common chassis for power, clock and trigger distribution, and data readout. As arrays become larger and reach several hundred channels, the readout electronics have to be divided over several chassis, but still must maintain precise synchronization of clocks and trigger signals across all channels. This division becomes necessary not only because of limits given by the instrumentation standards on module size and chassis slot numbers, but also because data readout times increase when more modules share the same data bus and because power requirements approach the limits of readily available power supplies. In this paper, we present a method for distributing clocks and triggers between 4 PXI chassis containing DGF Pixie-16 modules with up to 226 acquisition channels per chassis in a data acquisition system intended to instrument the over 600 channels of the SeGA detector array at the National Superconducting Cyclotron Laboratory. Our solution is designed to achieve synchronous acquisition of detector waveforms from all channels with a jitter of less then 1 ns, and can be extended to a larger number of chassis if desired.Comment: CAARI 200

LEVELS OF MUSCLE ACTIVATION IN STRENGTH AND CONDITIONING EXERCISES AND DYNAMOMETER HIKING IN JUNIOR SAILORS

This study recruited 29 (17 male and 12 female) high-level Byte class sailors aged 14-16 years to examine the average levels of muscle activation in lower limb and trunk muscles in four selected strength and conditioning exercises (leg extension, back squat and back extension exercises, a 30-second hiking hold) and a maximal three-minute hiking test (HM180). Results revealed that between-phase differences existed in the exercises examined. The level of muscle activation for the vastus lateralis for the leg extension exercise was shown to be comparable to that recorded during the back squat. Further, these exercises produced greater amounts of muscle activation when compared to those recorded during the HM180 test. Finally, the hiking hold produced greater levels of rectus abdominus activation when compared to the HM180 test

Radio Spectral Index and Expansion of 3C58

We present new observations of the plerionic supernova remnant 3C58 with the VLA at 74 and 327 MHz. In addition, we re-reduced earlier observations at 1.4 and 4.9 GHz taken in 1973 and 1984. Comparing these various images, we find that: 1. the remnant has a flat and relatively uniform spectral index distribution, 2. any expansion of the remnant with time is significantly less than that expected for uniform, undecelerated expansion since the generally accepted explosion date in 1181 A.D., and 3. there is no evidence for a non-thermal synchrotron emission shell generated by a supernova shock wave, with any such emission having a surface brightness of <1 x 10^(-21) W / (m^2 Hz sr) at 327 MHz.Comment: 18 pages, 7 Figures, Latex, Accepted for publication in the Astrophysical Journa

Self-aligned silicidation of surround gate vertical MOSFETs for low cost RF applications

We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for silicidation and is successfully integrated with a Fillet Local OXidation (FILOX) process, which thereby delivers low overlap capacitance and high drive-current vertical devices. Silicided 80-nm vertical n-channel devices fabricated using 0.5-?m lithography are compared with nonsilicided devices. A source–drain (S/D) activation anneal of 30 s at 1100 ?C is shown to deliver a channel length of 80 nm, and the silicidation gives a 60% improvement in drive current in comparison with nonsilicided devices. The silicided devices exhibit a subthreshold slope (S) of 87 mV/dec and a drain-induced barrier lowering (DIBL) of 80 mV/V, compared with 86 mV/dec and 60 mV/V for nonsilicided devices. S-parameter measurements on the 80-nm vertical nMOS devices give an fT of 20 GHz, which is approximately two times higher than expected for comparable lateral MOSFETs fabricated using the same 0.5-?m lithography. Issues associated with silicidation down the pillar sidewall are investigated by reducing the activation anneal time to bring the silicided region closer to the p-n junction at the top of the pillar. In this situation, nonlinear transistor turn-on is observed in drain-on-top operation and dramatically degraded drive current in source-on-top operation. This behavior is interpreted using mixed-mode simulations, which show that a Schottky contact is formed around the perimeter of the pillar when the silicided contact penetrates too close to the top S/D junction down the side of the pillar