Method and System for Downlink Transmission Scheduling in Multi-carrier Networks

A method of scheduling transmissions in a multi-carrier transmission system, includes, for each downlink transmission frame: partitioning the downlink transmission frame into a plurality of data regions each including an equal number of slots, each data region corresponding to a respective logical band; for a currently active connection: a) creating a first set of logical bands not fully occupied for transmission and having a minimum boosting level making the transmission receivable by a receiving terminal; b) extracting from the first set, a second set of logical bands available for allocating a maximum number of slots for downlink transmission to the active connection; and c) selecting the logical band for downlink transmission to the active connection from the second set as the logical band that, after allocating the slots to the considered connection, leaves a residual number of slots equal to or smaller than a predetermined minimum residual in the logical band, e.g., the smallest residual number of slots

Radiation tolerant IP Cores for the control and readout of front-end electronics in high energy physics experiments

In future HEP experiments the increased luminosity and the need of higher detector performance will push toward severe requirements on radiation hardness and power dissipation of hardware components. The use of "standard" and flexible protocols, modular architectures and IP-cores available to ASIC and FPGA designers will contribute to meet these requirements, while keeping development and production costs under control. The goal of the FF-LYNX project is the definition of a flexible protocol that allows the use of the same physical serial links and interfaces for the transmission of Timing, Trigger and Control (TTC) signals and Data Acquisition (DAQ). The protocol has been implemented in TX and RX interfaces based on serial electrical links designed as IP Cores. A test chip has been fabricated in the IBM 130nm CMOS technology. The architecture of the test interface and of the test chip will be presented together with preliminary results on area, speed and power consumption. Also the performance in terms of total ionization dose rad-tolerance will be reported. © 2011 IEEE

The FF-LYNX Project: Design of Fast and Flexible Protocols and HW Interfaces for Data Acquisition and TTC Distribution in High Energy Physics Experiments

The FF-LYNX project, aimed at the design of an innovative data transmission protocol for High Energy Physics experiments and its implementation in rad-hard, low-power interfaces, is described in this document. An outline of the present project status and results is presented, as well as the foreseen future activity

Radiation Tolerant IP Cores for the Control and Readout of Front-End Electronics in High Energy Physics Experiments

In future HEP experiments the increased luminosity and the need of higher detector performance will push toward severe requirements on radiation hardness and power dissipation of hardware components. The use of "standard" and flexible protocols, modular architectures and IP-cores available to ASIC and FPGA designers will contribute to meet these requirements, while keeping development and production costs under control. The goal of the FF-LYNX project is the definition of a flexible protocol that allows the use of the same physical serial links and interfaces for the transmission of Timing, Trigger and Control (TTC) signals and Data Acquisition (DAQ). The protocol has been implemented in TX and RX interfaces based on serial electrical links designed as IP Cores. A test chip has been fabricated in the IBM 130nm CMOS technology. The architecture of the test interface and of the test chip will be presented together with preliminary results on area, speed and power consumption. Also the performance in terms of total ionization dose rad-tolerance will be reported