7 research outputs found

    Rewriting System for Profile-Guided Data Layout Transformations on Binaries

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    International audienceCareful data layout design is crucial for achieving high performance. However exploring data layouts is time-consuming and error-prone, and assessing the impact of a layout transformation on performance is difficult without performing it. We propose to guide application programmers through data layout restructuring by providing a comprehensive multidimensional description of the initial layout, built from trace analysis, and then by giving a performance evaluation of the transformations tested and an expression of each transformed layout. The programmer can limit the exploration to layouts matching some patterns. We apply this method to two multithreaded applications. The performance prediction of multiple transformations matches within 5% the performance of hand-transformed layout code

    A Predictive Performance Model for Stencil Codes on Multicore CPUs

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    Exploiting SIMD and Thread-Level Parallelism in Multiblock CFD

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    Semi-automatic Composition of Data Layout Transformations for Loop Vectorization

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