Survey of techniques to reduce/minimize the control part/ROM of a microprogrammed digital computer

A survey was made of most of the important research to date on minimizing the control part of a microprogrammed digital computer. The results appear to be negative, i.e., the Glushkov and Schwartz approaches do not seem feasible in any practical environment. If the requirements of minimal solution are removed so that one would be satisfied with a near minimal solution, the integer programming method can be used since a very good solution is usually obtained after the ftrst iteration. (auth

Comments on capabilities, limitations, and correctness of Petri nets. Report 26

Petri nets were one of the earliest contributions to the theory of parallel computations and appear to be a natural way to represent the coordination of asynchronous events. Petri nets, however, are not restricted to modelling coordinates in computer systems. Any system where there are loosely connected essentially independent processes that proceed in an asynchronous marner can be modelled using Petri nets and should be useful in modelling business systems and biological systems. (MCW

A modeling approach and design tool for pipelined central processors

As CPUs have become larger and more complex, it has become increasingly more difficult during hardware design and implementation to predict how well a CPU will perform. Furthermore, buyers of such machines have a similar problem in evaluating CPU performance among a diverse selection of computers, since MIP rates quoted by manufacturers may be misleading. This paper describes a methodology based on simulation models for predicting the performance of central processors with instruction execution that occurs in distinct and separable phases. The basic components of the model have been designed to allow a functional representation of the instruction execution path. This provides a natural mapping of the instruction set onto the architecture in a manner familiar to the designer. The model has been verified for existing computers using actual trace data from these machines. Novel aspects of the model and its use in CPU design are discussed

A modeling approach and design tool for pipelined central processors

As CPUs have become larger and more complex, it has become increasingly more difficult during hardware design and implementation to predict how well a CPU will perform. Furthermore, buyers of such machines have a similar problem in evaluating CPU performance among a diverse selection of computers, since MIP rates quoted by manufacturers may be misleading. This paper describes a methodology based on simulation models for predicting the performance of central processors with instruction execution that occurs in distinct and separable phases. The basic components of the model have been designed to allow a functional representation of the instruction execution path. This provides a natural mapping of the instruction set onto the architecture in a manner familiar to the designer. The model has been verified for existing computers using actual trace data from these machines. Novel aspects of the model and its use in CPU design are discussed