High speed, scalable, and accurate implementation of packet fair queueing algorithms in ATM networks

The fluid Generalized Processor Sharing (GPS) algorithm has desirable properties for integrated services networks and many Packet Fair Queueing (PFQ) algorithms have been proposed to approximate GPS. However, there have been few high speed implementations of PFQ algorithms that can support large number of sessions with diverse rate requirements and at the same time maintain all the important properties of GPS. The implementation cost of a PFQ algorithm is determined by two components: (1) computation of the system virtual time function and (2) maintaining the relative ordering of the packets via their timestamps in a priority queue mechanism. While most of the recently proposed PFQ algorithms reduce the complexity of computing the system virtual time function, the complexity of maintaining the priority queue, and therefore the overall complexity of implementing PFQ, is still a function of the number of active sessions. In addition, while reducing the algorithmic or asymptotic complexity has been the focus of most analysis, to run at high speed, it is also important to reduce the complexity of basic operations. In this paper, we develop techniques to reduce both types of complexities. In particular, we present a novel grouping architecture for implementing PFQ with an algorithmtic complexity that is a function of the number of distinct rates supported, but independent of the number of sessions in the system. A key advantage of the proposed scheme is that it introduces only minor inaccuracy in the implemented algorithm. To reduce the cost of basic operations, we propose a hardware implementation framework and several novel techniques that reduce the on-chip memory size, offchip memory bandwidth, and off-chip access latency. We present a single chip implementation of WF   Q+, one of the most accurate Fair Queueing algorithms, that runs at 622 Mbps.