A CMOS 100 MHz continuous-time seventh order 0.05° equiripple linear phase leapfrog multiple loop feedback Gm-C filter

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”A novel 100 MHz CMOS Gm-C seventh-order 0.05° equiripple linear phase low-pass multiple loop feedback (MLF) filter based on leapfrog (LF) topology is presented. The filter is implemented using a fully-differential linear, high performance operational transconductance amplifier (OTA) based on cross-coupled pairs. PSpice simulations in a standard TSMC 0.25 μm CMOS process and with a single 5 V power supply have shown that the cut-off frequency of the filter without and with gain boost ranges from 8-32 MHz and 15-100 MHz, respectively. With gain boost, total harmonic distortion (THD) for a differential input voltage Vid of 315 mVpp at 1 MHz is less than -40 dB, dynamic range at 1% THD is over 55 dB, output noise with bandwidth 500 MHz is only 300 μVRMS, and power consumption is 322 mW

Single-amplifier integrator-based low power CMOS filter for video frequency applications

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”This paper describes a new low power fully differential second-order continuous-time low pass filter for use at video frequencies. The filter uses a single active device in combination with MOSFET resistors and grounded capacitors to achieve very low power consumption, small chip area and large dynamic range. The ideal integrator is realised using an internally compensated opamp consisting of only current mirrors and voltage buffers, whilst the lossy integrator is implemented by a single passive RC circuit. The filter has been simulated using a CMOS process. Results show that with a single 5 V power supply, cut-off frequency can be tuned from 3.5 MHz to 8 MHz, dynamic range is better than 67 dB, and power consumption is less than 1.7 mW

Hierarchical incremental class learning with reduced pattern training

Hierarchical Incremental Class Learning (HICL) is a new task decomposition method that addresses the pattern classification problem. HICL is proven to be a good classifier but closer examination reveals areas for potential improvement. This paper proposes a theoretical model to evaluate the performance of HICL and presents an approach to improve the classification accuracy of HICL by applying the concept of Reduced Pattern Training (RPT). The theoretical analysis shows that HICL can achieve better classification accuracy than Output Parallelism [1]. The procedure for RPT is described and compared with the original training procedure. RPT reduces systematically the size of the training data set based on the order of sub-networks built. The results from four benchmark classification problems show much promise for the improved model

China's Competition Policy Reforms: The Antimonopoly Law and Beyond

More than twelve years have elapsed since China began its efforts to enact a comprehensive antitrust law. Today, drafts of the law are still being debated. Such a protracted legislative process is highly unusual in China, and can only be explained by the controversy the draft law generates. After a brief review of China’s current competition policy, this paper discusses the fundamental issues in China’s economy that give rise to the challenges facing China’s antitrust policymakers in enacting the new antitrust law. These issues include the role of state-owned enterprises, perceived excessive competition in China’s economy, mergers and acquisitions by foreign companies, the treatment of administrative monopolies, and the enforcement of the antitrust law. While those controversies create significant policy issues for China, they do not constitute valid objections to the enactment of the new antitrust law. Meanwhile, it will be important for China to recognize that the new antitrust law alone will not be sufficient to fully realize its goal of promoting competition in its economy; other reforms will be necessary as well. China will be better off by moving swiftly to enact the new antitrust law, while keeping the momentum to engage in those other reforms.China, antitrust, law,