FREE RADICAL SCAVENGING ACTIVITY OF MARINE SPONGES COLLECTED FROM KOVALAM, CHENNAI

Objective: The main focus of this study is to screen the marine sponges for potent free radical scavenging activity. Methods: Various methods such as 2,2-diphenyl-1-picrylhydrazyl (DPPH), 2,2'-azino-bis(3-ethylbenzothiazoline-6-sulphonic acid) (ABTS), and ferric reducing antioxidant power (FRAP) assay are employed to ascertain the antioxidant properties of marine sponges namely Dysidea herbacea and Sigmadocia pumila. Results: On analyzing, the result of ABTS assay D. herbacea and S. pumila exhibited almost equal antioxidant properties. While calculating the inhibitory concentration 50% value for DPPH assay, the Sample 1 and 2 has an IC of 655.49 and 826.739 μl, respectively, and in FRAP assay, the Sample 1 and 2 has an IC of 67.587 and 74.57 μg, respectively. Conclusion: Overall from this assay, D. herbacea revealed slightly better antioxidant activity when compared to S. pumila, also which in future may serve as a better source to fight against various disease

Memory Bank and Register Allocation in Software Synthesis for ASIPs

An architectural feature commonly found in digital signal processors(DSPs) is multiple data-memory banks. This feature increases memory bandwidth by permitting multiple memory accesses to occur in parallel when the referenced variables belong to different memory banks and the registers involved are allocated according to a strict set of conditions. Unfortunately, current compiler technology is unable to take advantage of the potential increase in parallelism offered by such architectures. Consequently, most application software for DSP systems is hand-written -- a very time-consuming task. We present an algorithm which attempts to maximize the benefit of this architectural feature. While previous approaches have decoupled the phases of register allocation and memory bank assignment, our algorithm performs these two phasessimultaneously. Experimental results demonstrate that our algorithm substantially improves the code quality of many compiler-generated and even hand-written programs...

Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures

Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexed addressing mode, stack-allocated variables must be accessed by allocating address registers and performingaddress arithmetic. Subsuming address arithmetic into auto-increment/decrement arithmetic improves both the performance and size of the generated code. Our objective in this paper is to provide a method for comprehensively analyzing the performance benefits and hardware cost due to an auto-increment/decrement feature that varies from \Gammal to +l, and allowing access to k address registers in an address generator. We provide this method via a parameterizable optimization algorithm that operates on a procedure-wise basis. Hence, the optimization techniques in a compiler can be used not only to generate efficient or compact code, but also to help the designer of a custom DSP architecture make decisions on ad..

The Inktomi Climate Lab: An Integrated Environment for Analyzing and Simulating Customer Network Traffic

Abstract-- This paper describes the Inktomi Climate Lab, an inhouse environment that analyzes and simulates the HTTP traffic at our customer deployments. This lab is used to verify the stability and measure the performance of our web proxy cache, Inktomi Traffic Server 1, which has been deployed at many customer sites. The ability to support all HTTP headers, methods, and status codes, as well as features such as pipelining and chunked-encoding, enables our Climate Lab to accurately simulate any deployment. Having an in-house Climate Lab that is able to reproduce the network traffic at any customer site affords several benefits. For instance, it gives us the ability to thoroughly stress-test the software before deployment, thus ensuring its high quality and robustness in the field. Also, it gives us the ability to quickly reproduce and resolve software issues that do occur in the field. A

Optimization Of Embedded DSP Programs Using Post-Pass Data-Flow Analysis

We investigate the problem of code generation for DSP systems on a chip. Such systems devote a limited quantity of silicon to program ROM, so application software must be maximally dense. Additionally, the software must be written so as to meet various high-performance constraints, which may include hard real-time constraints. Unfortunately, current compiler technology is unable to generate dense, high-performance code for DSPs, whose architectures are highly irregular. Consequently, designers often resort to programming application software in assembly -- a time-consuming, error-prone, and non-portable task. Thus, DSP compiler technology must be improved substantially. We describe some optimizations that significantly improve the quality of compiler-generated code. Our optimizations are applied globally and even across procedure calls. Additionally, they are applied to the machine-dependent assembly representation of the source program. Our target architecture is the Texas Instruments..