Implementation and Use of SPFDs in Optimizing Boolean Networks

Yamashita et. al.[1] introduced a new category for expressing the flexibility that a node can have in a multi-level network. Originally presented in the context of FPGA synthesis, the paper has wider implications which were discussed in [2]. SPFDs are essentially a set of incompletely specified functions. The increased flexibility that they offer is obtained by allowing both a node to change as well as its immediate fanins. The challenge with SPFDs is (1) to compute them in an efficient way, and (2) to use their increased flexibility in a controlled way to optimize a circuit. In this paper, we provide a complete implementation of SPFDs using BDDs and apply it to the optimization of Boolean networks. Two scenarios are presented, one which trades literals for wires and the other rewires the network by replacing one fanin at a node by a new fanin. Results on benchmark circuits are very favorable. 1 Introduction At ICCAD'96, an interesting paper by Yamashita et. al. [1] was presented whi..

Implementation and Use of SPFDs in Optimizing Boolean Networks

Yamashita et. al.[1] introduced a new category for ex-pressing the flexibility that a node can have in a multi-level network. Originally presented in the context of FPGA syn-thesis, the paper has wider implications which were discussed in [2]. SPFDs are essentially a set of incompletely specified functions. The increased flexibility that they offer is obtained by allowing both a node to change as well as its immediate fanins. The challenge with SPFDs is (1) to compute them in an efficient way, and (2) to use their increased flexibility in a controlled way to optimize a circuit. In this paper, we provide a complete implementation of SPFDs using BDDs and apply it to the optimization of Boolean networks. Two scenarios are presented, one which trades literals for wires and the other rewires the network by replacing one fanin at a node by a new fanin. Results on benchmark circuits are very favorable.

SPFD-based wire removal in standard-cell and network-of-PLA circuits

Abstract—Wire removal is a technique by which the total number of wires between individual circuit nodes is reduced, either by removing wires or replacing them with other new wires. The wire removal techniques we describe in this paper are based on both binary and multivalued sets of pairs of functions to be distinguished (SPFDs). Recently, it was shown that a design style based on a multilevel network of approximately equal-sized programmable logic arrays (PLAs) results in a dense, fast, and crosstalk-resistant layout. This paper describes the application of SPFD-based wire removal techniques for circuit implementations utilizing networks of PLAs as well as standard-cells. In our first set of wire removal experiments (which utilize binary SPFD-based wire removal), we demonstrate that the benefit of SPFD-based wire removal is insignificant when the circuit is mapped using standard cells. We demonstrate that this technique is very effectiv

SPFD-based Wire Removal in a Network of PLAs

This paper describes the application of an SPFD-based wire removal technique for circuit implementations utilizing networks of PLAs. It has been shown that a design style based on a multi-level network of approximately equal-sized PLAs results in a dense, fast, and crosstalk-resistant layout. Wire removal is a technique where the total number of wires between individual circuit nodes is reduced, either by removing wires, or replacing them with other existing wires. The benefit of SPFD-based wire removal is shown to be insignificant when the circuit is mapped using standard cells. We demonstrate that this technique is very effective in the context of a network of PLAs. Further, we outline a technique for wire removal using multi-valued SPFDs which we expect will further improve the results