An organic integrated capacitive DC-DC up-converter

\u3cp\u3eIn this paper a fully integrated organic DC-DC upconverter is presented in a pentacene p-type only technology. This 3-stage Dickson converter reaches a voltage conversion factor of 3 for a purely capacitive load and 2.5 for a 10 μA load current. The maximal output voltage goes up to 75 V and the Dickson core efficiency is 48 %. The clock signal is generated on-chip with a 9-stage ring oscillator, built with zero-V\u3csub\u3egs\u3c/sub\u3e load inverters. A tunable input voltage provides a tuning range of 30 %. The presented converter is designed for the on-chip generation of voltages for biasing a capacitive load. This converter draws 560 μA from a 20 V supply voltage. The chip area measures 2.8x2.1 mm\u3csup\u3e2\u3c/sup\u3e. This converter fulfills a direct need for bias voltages beyond the supply voltage that is uncovered in recent work on organic circuits.\u3c/p\u3

Impact of etch stop layer on negative bias illumination stress of amorphous indium gallium zinc oxide transistors

\u3cp\u3eIn this work we show that the negative bias illumination stress (NBIS) of amorphous Indium Gallium Zinc Oxide (a-IGZO) transistors with an etch stop layer (ESL) deposited by physical vapor deposition (PVD) is substantially better than the NBIS of devices where the ESL layer is deposited by plasma enhanced chemical vapor deposition (PECVD). Both devices show similar transistor characteristics and bias stress in the dark but under NBIS conditions at 425 nm, PVD ESL based transistors show much less threshold voltage shift. The reduction in deep defects due to passivation by PVD layer is responsible for improved performance under NBIS.\u3c/p\u3

Designing flexible and stretchable circuits and displays

\u3cp\u3eAll technologies on flexible and stretchable foils suffer from intrinsic parameter variation. Designing for these technologies must start from a detailed analysis of these variations. Mapping these variations on the different design topologies that can be used to design flexible circuits, enables to predict and optimize the soft yield of these circuits. This methodology has been applied to designs of organic and oxide RFID and NFC tags, microprocessors on foil and also integrated linedrivers for displays.\u3c/p\u3

Flexible metal-oxide thin film transistor circuits for RFID and health patches

\u3cp\u3eWe discuss in this paper the present state and future perspectives of thin-film oxide transistors for flexible electronics. The application case that we focus on is a flexible health patch containing an analog sensor interface as well as digital electronics to transmit the acquired data wirelessly to a base station. We examine the electronic performance of amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) during mechanical bending. We discuss several ways to further boost the electronic transistor performance of n-type amorphous oxide semiconductors, by modifying the semiconductor or by improving the transistor architecture. We show analog and digital circuits constructed with several architectures, all based on n-type-only amorphous oxide technology. From circuit point of view, the discovery of a p-type amorphous semiconductor matching known n-type amorphous semiconductors would be of great importance. The present best-suited p-type is SnO, but it is poly-crystalline in nature and shows some ambipolarity due to the presence of n-type SnO2. In search of a better p-type semiconductor, preferably amorphous, we present recent insights into the band structure of potential amorphous oxide p-type semiconductors.\u3c/p\u3

Photolithography as enabler of AMOLED displays beyond 1000 ppi

\u3cp\u3eThis paper describes the potential of hi-res display fabrication using OLED photolithography. We demonstrate 1250 ppi multicolor arrays, pixel scaling down to 3 µm pitch, integration in active displays, and improving lifetime after patterning (200 hours T75, smOLEDs). Photolithography can enable low-cost, high resolution displays for the 8K - VR era.\u3c/p\u3

An inductively-coupled 64b organic RFID tag operating at 13.56MHz with a data rate of 787b/s

\u3cp\u3eA 64b inductively coupled organic RFID tag on foil is demonstrated at 13.56MHz. The digital logic foil comprises 414 pentacene transistors and is powered by a pentacene double half-wave rectifier, connected to an inductive antenna. The data rate is 787b/s with load modulation behind the rectifier (DC). Also shown is a functional AC-modulated organic RFID tag.\u3c/p\u3

Low-voltage gallium-indium-zinc-oxide thin film transistors based logic circuits on thin plastic foil:Building blocks for radio frequency identification application

\u3cp\u3eIn this work a technology to fabricate low-voltage amorphous gallium-indium-zinc oxide thin film transistors (TFTs) based integrated circuits on 25 μm foils is presented. High performance TFTs were fabricated at low processing temperatures (<150 °C) with field effect mobility around 17 cm\u3csup\u3e2\u3c/sup\u3e /V s. The technology is demonstrated with circuit building blocks relevant for radio frequency identification applications such as high-frequency functional code generators and efficient rectifiers. The integration level is about 300 transistors.\u3c/p\u3

Integrated line driver for digital pulse-width modulation driven AMOLED displays on flex

\u3cp\u3eAn integrated scan-line driver, driving half a QQVGA flexible AMOLED display using amorphous-IGZO backplane technology on foil, has been designed and measured. A pulse-width modulation technique has been implemented, enabling to drive the OLEDs with a duty cycle up to almost 100%. The digital driving method also results in a 40% static power reduction of the display. Dynamic logic and bootstrapping techniques enabled the use of clock frequencies up to 300kHz in unipolar amorphous-IGZO technologies on foil.\u3c/p\u3

Towards EPC-compatible organic RFID tags

\u3cp\u3eIn this chapter, fully integrated organic RFID tags are demonstrated. These tags are inductively-coupled at a base frequency of 13.56 MHz and can be read out at distances up to 10 cm, which is the expected readout distance for proximity readers. We also demonstrate next generation transponder chips, fabricated in a dual-gate technology. The additional gate, backgate, is used to control the threshold voltage and allows integration into more robust unipolar, dual-V\u3csub\u3eT\u3c/sub\u3e transponder chips. Finally, we realized an 8-bit transponder chip having data rates that are EPC-compatible. This has been achieved in our thin-film transistor technology by introducing a high-k Al\u3csub\u3e2\u3c/sub\u3eO \u3csub\u3e3\u3c/sub\u3e gate dielectric, by scaling the channel lengths down to 2 mm and by reducing the overlap capacitance of the parasitic source-gate and drain-gate capacitors.\u3c/p\u3