Poster: implications of merging phases on scalability of multi-core architectures

Amdahl's Law estimates parallel applications with negligible serial sections to potentially scale to many cores. However, due to merging phases in data mining applications, the serial sections do not remain constant. We extend Amdahl's model to accommodate this and establish that Amdahl's Law can overestimate the scalability offered by symmetric and asymmetric architectures for such applications. Implications: 1) A better use of the chip area is for fewer and hence more capable cores rather than simply increasing the number of cores for symmetric and asymmetric architectures and 2) The performance potential of asymmetric over symmetric multi-core architectures is limited for such applications

On Reconfigurable On-Chip Data Caches

Abstract Cache memory has shown to be the most important technique to bridge the gap between the processor speed and the memory access time. The advent of high-speed RISC and superscalar processors, however, calls for small on-chip data caches. Due to physical limitations, these should be simply designed and yet yield good performance. In this paper, we present new cache architectures that address the problems of conflict misses and non-optimal line sizes in the context of direct-mapped caches. Our cache architectures can be reconfigured by software in a way that matches the reference pattern for array data structures. We show that the implementation cost of the reconfiguration capability is neglectable. We also show simulation results !M demons tratc sign i fican t performance improvements for both methods

Poster: Implications of Merging Phases on Scalability of Multi-core Architectures

ABSTRACT Amdahl's Law estimates parallel applications with negligible serial sections to potentially scale to many cores. However, due to merging phases in data mining applications, the serial sections do not remain constant. We extend Amdahl's model to accommodate this and establish that Amdahl's Law can overestimate the scalability offered by symmetric and asymmetric architectures for such applications. Implications: 1) A better use of the chip area is for fewer and hence more capable cores rather than simply increasing the number of cores for symmetric and asymmetric architectures and 2) The performance potential of asymmetric over symmetric multi-core architectures is limited for such applications

Dating of two Paleolithic human fossil bones from Romania by accelerator mass spectrometry

In this study we have dated two human fossil remains found in Romania, by the method of radiocarbon using the technique of the accelerator mass spectrometry. The human fossil remains from Woman's cave, Baia deFier, have been dated to the age 30150 $\pm$ 800 years BP, and the skull from the Cioclovina cave has been dated to the age 29000 $\pm$ 700 years BP. These are the most ancient dated till now human fossil remains from Romania, possibly belonging to the upper Paleolithic, the Aurignacian period.Comment: 7 pages, 2 figures, presented to the Conference hipan2002, Neptum, Romania, 2-6 September 2002, http://idranap.nipne.ro/events/2002/HIPAN02/contents.ht

The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems

Abstract When supported in silicon, transactional memory (TM

A Robust Main-Memory Compression Scheme

Lossless data compression techniques can potentially free up more than 50 % of the memory resources. However, previously proposed schemes suffer from high access costs. The proposed main-memory compression scheme practically eliminates performance losses of previous schemes by exploiting a simple and yet effective compression scheme, a highly-efficient structure for locating a compressed block in memory, and a hierarchical memory layout that allows compressibility of blocks to vary with a low fragmentation overhead. We have evaluated an embodiment of the proposed scheme in detail using 14 integer and floating point applications from the SPEC2000 suite along with two server applications and we show that the scheme robustly frees up 30 % of the memory resources, on average, with a negligible impact on the performance of onl