On automatic generation of RTL validation test benches using circuit testing techniques

In this paper, we examine how good validation test benches can be auto-matically generated starting from the RTL description of a circuit. We de-velop our methodology based on extensive experiments performed with sev-eral popular benchmarks as well as industrial circuits. We try to leverage off a large body of work in the field of circuit testing and study how test sets de-rived for catching manufacturing defects fare from the standpoint of design validation. For this purpose, we perform an extensive empirical study using stuck-at test sets from gate-level implementations synthesized under various constraints. The experiments demonstrate that a good logic-level stuck-at test set is also an excellent RTL validation test bench. However, since we are dealing with RTL designs here and sequential logic-level ATPG is an expen-sive algorithm, we devise some methods to obtain good quality validation test vectors directly at the RTL. We use these results to enhance an existing RTL ATPG tool and show that test benches that can achieve good logic-level fault coverage and thus design validation coverage can be derived in our framework