Hierarchical Scheduling for Real-Time Periodic Tasks in Symmetric Multiprocessing

In this paper, we present a new hierarchical scheduling framework for periodic tasks in symmetric multiprocessor (SMP) platforms. Partitioned and global scheduling are the two main approaches used by SMP based systems where global scheduling is recommended for overall performance and partitioned scheduling is recommended for hard real-time performance. Our approach combines both the global and partitioned approaches of traditional SMP-based schedulers to provide hard real-time performance guarantees for critical tasks and improved response times for soft real-time tasks. Implemented as part of VxWorks, the results are confirmed using a real-time benchmark application, where response times were improved for soft real-time tasks while still providing hard real-time performance

ENLACE: What Makes a Difference in the Education of Latino US Students

In 1997, the W.K. Kellogg Foundation created a national education initiative, ENLACE (pronounced en-LAN-say), ENgaging LAtino Communities for Education. Its goal is to increase access and success in higher education for Latino students and their families. The $30 million investment in ENLACE by the Kellogg Eoundation responds to a timely need to connect all students to the possibilities of higher education. While the economy demands an increasingly educated and skilled workforce, the response of our educational system to meet this demand has been, most would agree, disjointed. Eor example, school districts define high school graduation requirements, while, often unconnected, the postsecondary system defines its own standards for college entrance. Thus, the K-12 school system and the higher education systems remain fragmented. Latino and other minority students, as well as students who are the first in their families with the possibility of college, suffer disproportionately from these disconnects. As these students complete high school, many are unprepared for college, as seen by the high demand for remedial classes, and often, ineligible for college, yet not even aware of this until their senior year. The roots of this disparity run deep. In the very early grades, students are tracked into either college-preparatory or remedial tracks, making it difficult to catch up in time for college. Despite these obstacles, research shows that the vast majority of students intend to go to college. ENLACE is a response to this disparity between Latino students' educational aspirations and their school career realities. ENLACE has forged connections between systems and thereby improved students' education possibilities, with a focus on the Latino community

Clock Gating Flip-Flop using Embedded XoR Circuitry

Flip flops/Pulsed latches are one of the main contributors of dynamic power consumption. In this paper, a novel flip-flop (FF) using clock gating circuitry with embedded XOR, GEMFF, is proposed. Using post layout simulation with 45nm technology, GEMFF outperforms prior state-of-the-art flip-flop by 25.1% at 10% data switching activity in terms of power consumption

On-Device Deep Learning Inference for System-on-Chip (SoC) Architectures

As machine learning becomes ubiquitous, the need to deploy models on real-time, embedded systems will become increasingly critical. This is especially true for deep learning solutions, whose large models pose interesting challenges for target architectures at the “edge” that are resource-constrained. The realization of machine learning, and deep learning, is being driven by the availability of specialized hardware, such as system-on-chip solutions, which provide some alleviation of constraints. Equally important, however, are the operating systems that run on this hardware, and specifically the ability to leverage commercial real-time operating systems which, unlike general purpose operating systems such as Linux, can provide the low-latency, deterministic execution required for embedded, and potentially safety-critical, applications at the edge. Despite this, studies considering the integration of real-time operating systems, specialized hardware, and machine learning/deep learning algorithms remain limited. In particular, better mechanisms for real-time scheduling in the context of machine learning applications will prove to be critical as these technologies move to the edge. In order to address some of these challenges, we present a resource management framework designed to provide a dynamic on-device approach to the allocation and scheduling of limited resources in a real-time processing environment. These types of mechanisms are necessary to support the deterministic behavior required by the control components contained in the edge nodes. To validate the effectiveness of our approach, we applied rigorous schedulability analysis to a large set of randomly generated simulated task sets and then verified the most time critical applications, such as the control tasks which maintained low-latency deterministic behavior even during off-nominal conditions. The practicality of our scheduling framework was demonstrated by integrating it into a commercial real-time operating system (VxWorks) then running a typical deep learning image processing application to perform simple object detection. The results indicate that our proposed resource management framework can be leveraged to facilitate integration of machine learning algorithms with real-time operating systems and embedded platforms, including widely-used, industry-standard real-time operating systems

Towards QoS-Based Embedded Machine Learning

Due to various breakthroughs and advancements in machine learning and computer architectures, machine learning models are beginning to proliferate through embedded platforms. Some of these machine learning models cover a range of applications including computer vision, speech recognition, healthcare efficiency, industrial IoT, robotics and many more. However, there is a critical limitation in implementing ML algorithms efficiently on embedded platforms: the computational and memory expense of many machine learning models can make them unsuitable in resource-constrained environments. Therefore, to efficiently implement these memory-intensive and computationally expensive algorithms in an embedded computing environment, innovative resource management techniques are required at the hardware, software and system levels. To this end, we present a novel quality-of-service based resource allocation scheme that uses feedback control to adjust compute resources dynamically to cope with the varying and unpredictable workloads of ML applications while still maintaining an acceptable level of service to the user. To evaluate the feasibility of our approach we implemented a feedback control scheduling simulator that was used to analyze our framework under various simulated workloads. We also implemented our framework as a Linux kernel module running on a virtual machine as well as a Raspberry Pi 4 single board computer. Results illustrate that our approach was able to maintain a sufficient level of service without overloading the processor as well as providing an energy savings of almost 20% as compared to the native resource management in Linux

The role of old-growth forests in frequent-fire landscapes

Classic ecological concepts and forestry language regarding old growth are not well suited to frequent-fire landscapes. In frequent-fire, old-growth landscapes, there is a symbiotic relationship between the trees, the understory graminoids, and fire that results in a healthy ecosystem. Patches of old growth interspersed with younger growth and open, grassy areas provide a wide variety of habitats for animals, and have a higher level of biodiversity. Fire suppression is detrimental to these forests, and eventually destroys all old growth. The reintroduction of fire into degraded frequent-fire, old-growth forests, accompanied by appropriate thinning, can restore a balance to these ecosystems. Several areas require further research and study: 1) the ability of the understory to respond to restoration treatments, 2) the rate of ecosystem recovery following wildfires whose level of severity is beyond the historic or natural range of variation, 3) the effects of climate change, and 4) the role of the microbial community. In addition, it is important to recognize that much of our knowledge about these old-growth systems comes from a few frequent-fire forest types

Vortex motion in axisymmetric piston-cylinder configurations

Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/76950/1/AIAA-8430-329.pd

The Signal Sequence Coding Region Promotes Nuclear Export of mRNA

In eukaryotic cells, most mRNAs are exported from the nucleus by the transcription export (TREX) complex, which is loaded onto mRNAs after their splicing and capping. We have studied in mammalian cells the nuclear export of mRNAs that code for secretory proteins, which are targeted to the endoplasmic reticulum membrane by hydrophobic signal sequences. The mRNAs were injected into the nucleus or synthesized from injected or transfected DNA, and their export was followed by fluorescent in situ hybridization. We made the surprising observation that the signal sequence coding region (SSCR) can serve as a nuclear export signal of an mRNA that lacks an intron or functional cap. Even the export of an intron-containing natural mRNA was enhanced by its SSCR. Like conventional export, the SSCR-dependent pathway required the factor TAP, but depletion of the TREX components had only moderate effects. The SSCR export signal appears to be characterized in vertebrates by a low content of adenines, as demonstrated by genome-wide sequence analysis and by the inhibitory effect of silent adenine mutations in SSCRs. The discovery of an SSCR-mediated pathway explains the previously noted amino acid bias in signal sequences and suggests a link between nuclear export and membrane targeting of mRNAs

Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer

In the modern graphics processing unit (GPU)/artificial intelligence (AI) era, flip-flop (FF) has become one of the most power-hungry blocks in processors. To address this issue, a novel single-phase-clock dual-edge-triggering (DET) FF using a single-transistor-clocked (STC) buffer (STCB) is proposed. The STCB uses a single-clocked transistor in the data sampling path, which completely removes clock redundant transitions (RTs) and internal RTs that exist in other DET designs. Verified by post-layout simulations in 22 nm fully depleted silicon on insulator (FD-SOI) CMOS, when operating at 10% switching activity, the proposed STC-DET outperforms prior state-of-the-art low-power DET in power consumption by 14% and 9.5%, at 0.4 and 0.8 V, respectively. It also achieves the lowest power-delay-product (PDP) among the DETs