PCNNA: A Photonic Convolutional Neural Network Accelerator

Convolutional Neural Networks (CNN) have been the centerpiece of many applications including but not limited to computer vision, speech processing, and Natural Language Processing (NLP). However, the computationally expensive convolution operations impose many challenges to the performance and scalability of CNNs. In parallel, photonic systems, which are traditionally employed for data communication, have enjoyed recent popularity for data processing due to their high bandwidth, low power consumption, and reconfigurability. Here we propose a Photonic Convolutional Neural Network Accelerator (PCNNA) as a proof of concept design to speedup the convolution operation for CNNs. Our design is based on the recently introduced silicon photonic microring weight banks, which use broadcast-and-weight protocol to perform Multiply And Accumulate (MAC) operation and move data through layers of a neural network. Here, we aim to exploit the synergy between the inherent parallelism of photonics in the form of Wavelength Division Multiplexing (WDM) and sparsity of connections between input feature maps and kernels in CNNs. While our full system design offers up to more than 3 orders of magnitude speedup in execution time, its optical core potentially offers more than 5 order of magnitude speedup compared to state-of-the-art electronic counterparts.Comment: 5 Pages, 6 Figures, IEEE SOCC 201

Temperature Dependence of a Sub-wavelength Compact Graphene Plasmon-Slot Modulator

We investigate a plasmonic electro-optic modulator with an extinction ratio exceeding 1 dB/um by engineering the optical mode to be in-plane with the graphene layer, and show how lowering the operating temperature enables steeper switching. We show how cooling Graphene enables steeping thus improving dynamic energy consumption. Further, we show that multi-layer Graphene integrated with a plasmonic slot waveguide allows for in-plane electric field components, and 3-dB device lengths as short as several hundred nanometers only. Compact modulators approaching electronic length-scales pave a way for ultra-dense photonic integrated circuits with smallest footprint

Integrated Photonic Tensor Processing Unit for a Matrix Multiply: a Review

The explosion of artificial intelligence and machine-learning algorithms, connected to the exponential growth of the exchanged data, is driving a search for novel application-specific hardware accelerators. Among the many, the photonics field appears to be in the perfect spotlight for this global data explosion, thanks to its almost infinite bandwidth capacity associated with limited energy consumption. In this review, we will overview the major advantages that photonics has over electronics for hardware accelerators, followed by a comparison between the major architectures implemented on Photonics Integrated Circuits (PIC) for both the linear and nonlinear parts of Neural Networks. By the end, we will highlight the main driving forces for the next generation of photonic accelerators, as well as the main limits that must be overcome