Reusable Verification Environment for a RISC-V Vector Accelerator

This paper presents a reusable verification environment developed for the verification of an academic RISC-V based vector accelerator that operates with long vectors. In order to be used across diverse projects, this infrastructure intends to be independent of the interface used for connecting the accelerator to the scalar processor core. We built a verification infrastructure consisting of a Universal Verification Environment (UVM) which is capable of validating the design performing co-simulation of the vector instructions. Moreover, we provided a set of tests and an automated test generation, simulation and error reporting infrastructure. This paper shares our experience on verifying a complex accelerator used in two distinct projects, with different interfaces.This research has received funding from the European High Performance Computing Joint Undertaking (JU) under Framework Partnership Agreement No 800928 (European Processor Initiative) and Specific Grant Agreement No 101036168 (EPI SGA2) and No 956702 (eProcessor) . The JU receives support from the European Union’s Horizon 2020 research and innovation programme and from Croatia, France, Germany, Greece, Italy, Netherlands, Portugal, Spain, Sweden, and Switzerland. The EPI-SGA2 project, PCI2022-132935_N1618737 is also co-funded by MCIN/AEI /10.13039/501100011033 and by the UE NextGenerationEU/PRTRPeer ReviewedPostprint (author's final draft