Run-time adaptation of a reconfigurable mobile UMTS receiver

UMTS receivers are mobile devices, which should have a low energy consumption and operates in a frequently changing environment. The idea of this paper is to adapt the amount of signal processing for the reception within an UMTS mobile to this changing environment. In this way the amount of signal processing can be decreased for a good channel to decrease the energy consumption and for a bad channel the signal processing can be increased to guarantee a minimum Quality of Service for the signal. Due to space limitation, this paper only describes the approach. For full details see [1]

Run-time Energy Management for Mobiles

Due to limited energy resources, mobile computing requires an energy-efficient a rchitecture. The dynamic nature of a mobile environment demands an architecture that allows adapting to (quickly) changing conditions. The mobile has to adapt d ynamically to new circumstances in the best suitable manner. The hardware and so ftware architecture should be able to support such adaptability and minimize the energy consumption by making resource allocation decisions at run-time. To make these decisions effective, a tradeoff has to be made between computation , communication and initialization costs (both time and energy). This paper describes our approach to construct a model that supports taking such decisions

Energy-efficient wireless communication for mobile multimedia terminals

This paper presents a control system that adapts a WCDMA receiver at run-time to minimize the energy consumption while providing an adequate Quality of Service (QoS). The adaptation is done at run-time, because of the dynamic environment of a mobile receiver. Simulations show that run-time adaptation to the environment decreases the energy consumption of a receiver and also improves other QoS parameters, such as a higher throughput and a lower frame error rate

Run-time Mapping of Applications to a Heterogeneous SoC

This paper presents an iterative hierarchical approach to map an application to a parallel heterogeneous SoC architecture at run-time. The application is modeled as a set of communicating processes. The optimization objective is to minimize the energy consumption of the SoC, while still providing the required Quality of Service. This approach is flexible, scalable and the performance looks promisin

BER estimation for wireless links using BPSK/QPSK modulation

This paper introduces a method that computes an estimation of the bit error rate (BER) based on the RAKE receiver soft output only. For this method no knowledge is needed about the channel characteristics nor the precise external conditions. Simulations show that the mean error of the estimation is below 2%, with only a small variance. Also an estimation of the BER for a different spreading factor or a different number of RAKE finger can be made. Implementation issues for a practical use of the method are discussed

An Energy-Efficient Reconfigurable Circuit Switched Network-on-Chip

Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for multi-tile System-on-Chip (SoC) architectures. The SoC architecture, including its run-time software, can replace inflexible ASICs for future ambient systems. These ambient systems have to be flexible as well as energy-efficient. To find an energy-efficient solution for the communication network we analyze three wireless applications. Based on their communication requirements we observe that revisiting of the circuit switching techniques is beneficial. In this paper we propose a new energy-efficient reconfigurable circuit-switched Network-on-Chip. By physically separating the concurrent data streams we reduce the overall energy consumption. The circuit-switched router has been synthesized and analyzed for its power consumption in 0.13 ¿m technology. A 5-port circuit-switched router has an area of 0.05 mm2 and runs at 1075 MHz. The proposed architecture consumes 3.5 times less energy compared to its packet-switched equivalen

Soft output bit error rate estimation for WCDMA

This paper introduces a method that computes an estimation of the bit error rate (BER) based on the RAKE receiver soft output only. For this method no knowledge is needed about the channel characteristics nor the precise external conditions. Simulations show that the mean error of the estimation is below 2%, with only a small variance. Implementation issues for a practical use of the method are discussed

Mapping the SISO module of the Turbo decoder to a FPFA

In the CHAMELEON project a reconfigurable systems-architecture, the Field Programmable Function Array (FPFA) is introduced. FPFAs are reminiscent to FPGAs, but have a matrix of ALUs and lookup tables instead of Configurable Logic Blocks (CLBs). The FPFA can be regarded as a low power reconfigurable accelerator for an application specific domain. In this paper we show how the SISO (Soft Input Soft Output) module of the Turbo decoding algorithm can be mapped on the reconfigurable FPFA