A low-power analog logarithmic map circuit with offset and temperature compensation for use in bionic ears

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 74-75).This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Logarithmic map circuits are useful in many applications that require non-linear signal compression, such as in speech recognition and cochlear implants. A logarithmic current-mode A/D converter with temperature compensation and automatic offset calibration is presented in this paper. It employs a dual-slope, auto-zeroing topology with a 60 dB dynamic range and 300 Hz sampling rate, for capturing the envelope of speech signals in a bionic ear. Fabricated in a 1.5 [mu]m process, the circuit consumes only 1 [mu]W of analog power and another 1 [mu]W of digital power, and can therefore run for over 50 years on just a couple of AA batteries. At the current level of power consumption, we have proven that this design is thermal-noise limited to a 6-bit precision, and higher precision is possible only if we expend more power. As such, it is already useful for cochlear implants, as deaf patients can only discriminate 1 dB out of a 30 dB dynamic range in the auditory nerve bundles. For the purpose of using this circuit in other applications, we conclude with several strategies that can increase the precision without hurting the power consumption.by Ji-Jon Sit.S.M

An asynchronous,low-power architecture for interleaved neural stimulation, using envelope and phase information

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 122-124).This thesis describes a low-power cochlear-implant processor chip and a charge-balanced stimulation chip that together form a complete processing-and-stimulation cochlear-implant system. The processor chip uses a novel Asynchronous Interleaved Stimulation (AIS) algorithm that preserves phase and amplitude cues in its spectral input while simultaneously minimizing electrode interactions and lowering average stimulation power per electrode. The stimulator chip obviates the need for large D.C. blocking capacitors in neural implants to achieve highly precise charge-balanced stimulation, thus lowering the size and cost of the implant. Thus, this thesis suggests that significant performance, power and cost improvements in the current generation of cochlear implants may be simultaneously possible. The 16-channel ~90 square mm AIS processor chip was built in a 1.5[mu]m VLSI process and consumed 107[mu]W of power over and above that of its analog spectral processing front end, which consumed 250gtW and which has been previously described. The AIS processor was found to faithfully mimic MATLAB implementations of the AIS algorithm. Two perceptual tests of the AIS algorithm with normal-hearing listeners verified that AIS signal reconstructions enabled better melody and speech recognition in noise than traditional envelope-only vocoder simulations of cochlear-implant processing. The average firing rate of the AIS processor was found to be significantly lower than in traditional synchronous stimulators, suggesting that the AIS algorithm and processor can potentially save power and improve hearing performance in cochlear-implant users. The stimulator chip was built in a 0.7glm high-voltage VLSI process and performed dynamic current balancing followed by a shorting phase.(cont.) It achieved <6nA of average DC current error, well below the targeted safety limit of 25nA for cochlear-implant patients. On +6 and -9V rails, the power consumption of a single channel of this chip was 47[mu]W when biasing power is shared by 16 channels. It puts out a charge-balanced stimulation pulse whenever it receives an asynchronous input signal from an AIS processor encoding phase information and 7-bit amplitude information, thus making the AIS processor chip and stimulator chip fully compatible in the cochlear-implant system. The AIS algorithm and charge-balancing circuits described in this work may be useful in other nerve-stimulation prosthetics where good fidelity in input-information encoding, minimization of electrode interactions, low-power strategies for stimulation, and compact charge-balanced stimulation are also important.by Ji-Jon Sit.Ph.D