Voltage-Pulse Driven Harmonic Resonant Rail Drivers for Low-Power Applications

Abstract—We describe a new design technique for efficient harmonic resonant rail drivers. The proposed circuit implementation is coupled to a standard pulse source and uses only discrete passive components and no external dc power supply. It can thus be externally tuned to minimize the consumed power in the target IC. A new design technique based on current-fed voltage pulse-forming network theory is proposed to find the value of each discrete component for a target frequency and a given load capacitance. The proposed circuit topology can be used to generate any desired periodic 50 % duty-cycle waveform by superimposing multiple harmonics of the desired waveform, however, this paper focuses on the generation of trapezoidal-wave clock signals. We have tested the driver with a capacitive load between 38.3 and 97.8 pF with clock frequency ranging between 0.8 and 15 MHz. The overall power dissipation for our second-order harmonic rail driver is 19 % of P at 15 MHz and 97.8 pF load. Index Terms—Clock generator, energy-recovery circuit, harmonic resonance, low power. I

The use of interaural time and level difference cues by bilateral cochlear implant users

While considerable evidence suggests that bilateral cochlear implant (CI) users’ sound localization abilities rely primarily on interaural level difference (ILD) cues, and only secondarily, if at all, on interaural time difference (ITD) cues, this evidence has largely been indirect. This study used head-related transfer functions (HRTFs) to independently manipulate ITD and ILD cues and directly measure their contribution to bilateral CI users’ localization abilities. The results revealed a strong reliance on ILD cues, but some CI users also made use of ITD cues. The results also suggest a complex interaction between ITD and ILD cues

Band-limite fed-li kcanceGE)3OO with amodifie filtee d-X LMS algorithm forheGj3( aids

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