A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

A slope analog-to-digital converter (ADC) amenable to be fully implemented on a digital field programmable gate array (FPGA) without requiring any external active or passive components is proposed in this paper. The amplitude information, encoded in the transition times of a standard LVDS differential input—driven by the analog input and by the reference slope generated by an FPGA output buffer—is retrieved by an FPGA time-to-digital converter. Along with the ADC, a new online calibration algorithm is developed to mitigate the influence of process, voltage, and temperature variations on its performance. Measurements on an ADC prototype reveal an analog input range from 0.3 V to 1.5 V, a least significant bit (LSB) of 2.6 mV, and an effective number of bits (ENOB) of 7.4-bit at 600 MS/s. The differential nonlinearity (DNL) is in the range between −0.78 and 0.70 LSB, and the integral nonlinearity (INL) is in the range from −0.72 to 0.78 LSB

An Ultra-Small Area and High-Sensitivity Wireless Receiver for ISM and MICS Band Application

In this work, a 0.43mm2 high-sensitivity low-intermediate-frequency (low-IF) receiver under $0.18~\mu \text{m}$ technology is reported for Industrial Scientific Medical (ISM) and Medical Implant Communications Service (MICS) band applications, which supports the 2ASK/GFSK demodulation mode. To reduce the area, a low noise amplifier (LNA) with an active inductor, a compact Gm-C filter, an AC current bleeding technique for controlling the receiver gain and, a ring-VCO LO PLL were used, without any passive inductors. The main methods for improving sensitivity are reducing the receiver noise figure (NF) and improving the signal-to-noise ratio for demodulation. Thus, the LNA adopts a two-stage 40 dB gain to suppress the NF of the subsequent stage. An automatic gain control (AGC) loop is used to control the receiver gain to overcome the large signal nonlinearity from the large LNA gains. Additionally, a Gm-C complex filter rejects image and blocks interference, improving the sensitivity to harsh environments. Under the CSMC $0.18~\mu \text{m}$ process, the die of the receiver is only 0.43 mm2 and covers 300–500 MHz, MICS and some ISM bands. The measurement results show that when the internal 2ASK demodulator is adopted, it has a −115 dBm sensitivity at 2 Kbps; and when the external GFSK digital baseband is adopted, it has a −121 dBm sensitivity at 2 Kbps. At 300 Kbps, only 6.5 mW of power is consumed. It is suitable for low-power wide-area network (LPWAN) applications

An Energy and Area Efficient Carry Select Adder with Dual Carry Adder Cell

In this paper, an energy and area efficient carry select adder (CSLA) is proposed. To minimize the redundant logic operation of a regular CSLA, a dual carry adder cell is proposed. The proposed dual carry adder is composed of an XOR/XNOR cell and two pairs of sum-carry cells. Both CMOS logic and a transmission gate were applied to the dual carry adder cell to achieve fast and energy efficient operation. Eight-bit, 16b, and 32b square-root (SQRT) CSLAs based on the proposed dual carry adder were developed. The post-layout simulation based on a SMIC 55 nm process demonstrated that the proposed CSLAs reduced power consumption by 68.4–72.2% with a slight delay increase for different bit widths. As the dual carry adder had much fewer transistors than the two regular full adders, the area of the proposed CSLAs was reduced by 45.8–51.1%. The area-power-delay product of the proposed CSLA improved 5.1×–6.73× compared with the regular CSLA

Research on Cosine-Sum Windows with Maximum Side-Lobe Decay for High Precision ADC Spectral Testing

Achieving coherent sampling has always been a major challenge in analog-to-digital converter (ADC) spectral testing. If the coherent sampling condition cannot be met, leakage appears in the spectrum, which results in inaccurate parameters. The windowing method is widely used to process ADC data to eliminate leakage. However, this method requires prior knowledge about the type of window, and some commonly used windows cannot provide accurate results for a high precision ADC. In this paper, some general principles for optimizing the cosine-sum window and some windows with maximum side-lobe decay have been presented. A test method for eliminating the leakage caused by non-coherent sampling is also proposed. The proposed method can accurately evaluate the dynamic parameters of an ADC with arbitrary non-coherency. Various simulation results and measurement data demonstrate the functionality and robustness of the proposed method. The proposed method significantly relaxes the condition of coherent sampling and decreases the test cost

An Energy-Efficient Level Shifter for Ultra Low-Voltage Digital Lsis

This brief presents a fast and energy-efficient level shifter with wide conversion range. To achieve both energy-efficient and high-speed voltage level conversion, a novel architecture combined with multi-threshold CMOS technique is employed in the proposed circuit. A mixed-threshold current mirror circuit is proposed to solve the reduced swing issue in the prior arts. Moreover, auxiliary bias circuits are inserted to guarantee that the low-threshold pull down networks could be strongly cut off while in leaking state. As a result, the power consumption would be reduced to a great extent. Measurement results based on SMIC 55-nm MTCMOS process demonstrate that the proposed level shifter could provide robust voltage conversion from 0.12V to 1.2V. At the target voltage of 0.3V, the proposed level shifter shows a propagation delay of 17.86ns, a static power of 73.95pW, and an energy per transition of 26.59fJ for input frequency of 1MHz

Low Computing Leakage, Wide-Swing Output Compensation Circuit for Linearity Improvement in SRAM Multi-Row Read Computing-in-Memory

To increase the throughput of computing-in-memory (CIM) designs, multi-row read methods have been adopted to increase computation in the analog region. However, the nonlinearity created by doing so degrades the precision of the results obtained. The results of CIM computation need to be precise in order for CIM designs to be used in machine learning circumstances involving complex algorithms and big data sets. In this study, a low computing leakage, wide-swing output compensation circuit is proposed for linearity improvement in such circumstances. The proposed compensation circuit is composed of a current competition circuit (as dynamic feedback of the bitline discharge current), a current mirror (to separate the result capacitor and provide charge current), and an additional pull-down circuit (for better precision in high voltage results). Measurements show that by applying our method, an almost full-swing output with 51.2% nonlinearity decrement compared with no compensation can be achieved. Power consumption is reduced by 36% per round on average and the computing leakage current, after wordlines are deactivated for 1 ns, is reduced to 55% of that when using conventional methods. A figure of merit (FOM) is proposed for analog computing module evaluation, presenting a comprehensive indicator for the computation precision of such designs

An 8-Gbps, Low-Jitter, Four-Channel Transmitter with a Fractional-Spaced Feed-Forward Equalizer

An 8 gigabits per second (Gbps), low-jitter, four-channel transmitter with fractional-spaced feed-forward equalizer (FFE) is designed to meet the demand for broad transmission bandwidth in serial data communications. A novel frequency divider chain (FDC) architecture is developed, to satisfy the time requirements for high-speed data serialization. Moreover, a reconfigurable output driver circuit is employed to ensure compatibility with different protocols. In addition, a three-tap fractional-spaced FFE, which can enhance signal bandwidth significantly, is proposed, to compensate for channel loss. The transmitter was simulated and validated based on the Semiconductor Manufacturing International Corporation (SMIC) 55-nm process. The post-layout simulation results show the following: The tuning range of the phase-locked loop (PLL) can cover 1.6 to 4.6 GHz. At an output frequency of 4 GHz, the root-mean-square jitter (RJ) of the PLL after integration from phase noise was 1.93 ps. With an 8 Gbps output data rate, using the pseudo-random binary sequence (PRBS)-31 as a data source to simulate the whole transmitter, the power consumption values of the PLL and drive circuit were 27.0 and 29.2 mW, respectively, and the eye width and the valid eye height of output data were 0.76 unit interval (UI) and 0.68

An 8-Gbps, Low-Jitter, Four-Channel Transmitter with a Fractional-Spaced Feed-Forward Equalizer

An 8 gigabits per second (Gbps), low-jitter, four-channel transmitter with fractional-spaced feed-forward equalizer (FFE) is designed to meet the demand for broad transmission bandwidth in serial data communications. A novel frequency divider chain (FDC) architecture is developed, to satisfy the time requirements for high-speed data serialization. Moreover, a reconfigurable output driver circuit is employed to ensure compatibility with different protocols. In addition, a three-tap fractional-spaced FFE, which can enhance signal bandwidth significantly, is proposed, to compensate for channel loss. The transmitter was simulated and validated based on the Semiconductor Manufacturing International Corporation (SMIC) 55-nm process. The post-layout simulation results show the following: The tuning range of the phase-locked loop (PLL) can cover 1.6 to 4.6 GHz. At an output frequency of 4 GHz, the root-mean-square jitter (RJ) of the PLL after integration from phase noise was 1.93 ps. With an 8 Gbps output data rate, using the pseudo-random binary sequence (PRBS)-31 as a data source to simulate the whole transmitter, the power consumption values of the PLL and drive circuit were 27.0 and 29.2 mW, respectively, and the eye width and the valid eye height of output data were 0.76 unit interval (UI) and 0.68