IGNSS Society 2013 Symposium Proceedings

The continuing expansion of available GNSS signals is an increasingchallenge for receiver designers. New signals with expandedbandwidths are demanding greater sampling rates that require carefuldesign of the receiver RF section to maximise performance tradeoffs. Ahigh level of integration is required to preserve signal path integrity andminimise noise while keeping power consumption to a minimum. Thedesign of the frequency plan and the choice of IF bandwidth are criticalto overall receiver performance. This paper describes the developmentof the monolithic RF front end chips used in the new Namuru multi-GNSS receivers at UNSW. Analysis of the system requirements andarchitecture design are discussed including the LNA, Mixer, IFAmplifier through to the A/D converter. The re-configurable designprovides frequency plan and signal selection flexibility using anintegrated synthesiser and programmable bandwidth filter. The designchallenges of the new front end chips are discussed including featuresaimed at delivering greater performance and flexibility