284 research outputs found
Memory and information processing in neuromorphic systems
A striking difference between brain-inspired neuromorphic processors and
current von Neumann processors architectures is the way in which memory and
processing is organized. As Information and Communication Technologies continue
to address the need for increased computational power through the increase of
cores within a digital processor, neuromorphic engineers and scientists can
complement this need by building processor architectures where memory is
distributed with the processing. In this paper we present a survey of
brain-inspired processor architectures that support models of cortical networks
and deep neural networks. These architectures range from serial clocked
implementations of multi-neuron systems to massively parallel asynchronous ones
and from purely digital systems to mixed analog/digital systems which implement
more biological-like models of neurons and synapses together with a suite of
adaptation and learning mechanisms analogous to the ones found in biological
nervous systems. We describe the advantages of the different approaches being
pursued and present the challenges that need to be addressed for building
artificial neural processing systems that can display the richness of behaviors
seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed
neuromorphic computing platforms and system
Hardware-Amenable Structural Learning for Spike-based Pattern Classification using a Simple Model of Active Dendrites
This paper presents a spike-based model which employs neurons with
functionally distinct dendritic compartments for classifying high dimensional
binary patterns. The synaptic inputs arriving on each dendritic subunit are
nonlinearly processed before being linearly integrated at the soma, giving the
neuron a capacity to perform a large number of input-output mappings. The model
utilizes sparse synaptic connectivity; where each synapse takes a binary value.
The optimal connection pattern of a neuron is learned by using a simple
hardware-friendly, margin enhancing learning algorithm inspired by the
mechanism of structural plasticity in biological neurons. The learning
algorithm groups correlated synaptic inputs on the same dendritic branch. Since
the learning results in modified connection patterns, it can be incorporated
into current event-based neuromorphic systems with little overhead. This work
also presents a branch-specific spike-based version of this structural
plasticity rule. The proposed model is evaluated on benchmark binary
classification problems and its performance is compared against that achieved
using Support Vector Machine (SVM) and Extreme Learning Machine (ELM)
techniques. Our proposed method attains comparable performance while utilizing
10 to 50% less computational resources than the other reported techniques.Comment: Accepted for publication in Neural Computatio
Continuous-time adaptive delay system
We have developed a direction-selective system that has a row of pixels with photodiodes as the front-end. The output of each photodiode is converted to a digital signal, which is then fed to an adaptive-delay block within each pixel. The adaptive block adjusts an internal delay such that the delay matches the phase offset between the rising edges of this digital signal and the corresponding digital signal from the neighboring pixel. The system does this delay matching by using a dynamic current source to adapt the bias voltage that controls the delay. The adaptive-delay block is similar to a digital charge-pump phase-lock loop (PLL). It differs from conventional PLL's however, both in its compact size and its lack of a system clock. It also has a fast pull-in time during the locking of the signal. Since our application does not require low jitter, we have not introduced a phase offset in the comparator as is typically done in PLLs. The transistors here are operated In subthreshold. A stability analysis of the feedback system leads to simple stability and convergence constraints. Experimental results from circuits fabricated in 2 μm CMOS technology show that the circuit can lock over 5 decades of frequency
Continuous-time adaptive delay system
We have developed an adaptive delay system that adjusts the delay of a delay element so that it matches the temporal disparity between the onset of two input signals. The delay is controlled either by an external bias voltage, or by an intrinsic signal derived from an adaptive block. The operation of the adaptive delay system is similar to that of a charge-pump phase-lock loop, with an extended lock-in range of more than 5 decades. Standard CMOS transistors are used in their subthreshold region. Experimental results from circuits fabricated in 2 μm CMOS technology are in agreement with the analysi
DDD17: End-To-End DAVIS Driving Dataset
Event cameras, such as dynamic vision sensors (DVS), and dynamic and
active-pixel vision sensors (DAVIS) can supplement other autonomous driving
sensors by providing a concurrent stream of standard active pixel sensor (APS)
images and DVS temporal contrast events. The APS stream is a sequence of
standard grayscale global-shutter image sensor frames. The DVS events represent
brightness changes occurring at a particular moment, with a jitter of about a
millisecond under most lighting conditions. They have a dynamic range of >120
dB and effective frame rates >1 kHz at data rates comparable to 30 fps
(frames/second) image sensors. To overcome some of the limitations of current
image acquisition technology, we investigate in this work the use of the
combined DVS and APS streams in end-to-end driving applications. The dataset
DDD17 accompanying this paper is the first open dataset of annotated DAVIS
driving recordings. DDD17 has over 12 h of a 346x260 pixel DAVIS sensor
recording highway and city driving in daytime, evening, night, dry and wet
weather conditions, along with vehicle speed, GPS position, driver steering,
throttle, and brake captured from the car's on-board diagnostics interface. As
an example application, we performed a preliminary end-to-end learning study of
using a convolutional neural network that is trained to predict the
instantaneous steering angle from DVS and APS visual data.Comment: Presented at the ICML 2017 Workshop on Machine Learning for
Autonomous Vehicle
Kernel Modulation: A Parameter-Efficient Method for Training Convolutional Neural Networks
Deep Neural Networks, particularly Convolutional Neural Networks (ConvNets),
have achieved incredible success in many vision tasks, but they usually require
millions of parameters for good accuracy performance. With increasing
applications that use ConvNets, updating hundreds of networks for multiple
tasks on an embedded device can be costly in terms of memory, bandwidth, and
energy. Approaches to reduce this cost include model compression and
parameter-efficient models that adapt a subset of network layers for each new
task. This work proposes a novel parameter-efficient kernel modulation (KM)
method that adapts all parameters of a base network instead of a subset of
layers. KM uses lightweight task-specialized kernel modulators that require
only an additional 1.4% of the base network parameters. With multiple tasks,
only the task-specialized KM weights are communicated and stored on the
end-user device. We applied this method in training ConvNets for Transfer
Learning and Meta-Learning scenarios. Our results show that KM delivers up to
9% higher accuracy than other parameter-efficient methods on the Transfer
Learning benchmark.Comment: Accepted at 2022 26th International Conference on Pattern Recognition
(ICPR
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