16 research outputs found
VoltageIsland Driven Floorplanning Considering Level-Shifter Positions. GLSVLSI
ABSTRACT Power optimization has become a significant issue when the CMOS technology entered the nanometer era. MultipleSupply Voltage (MSV) is a popular and effective method for power reduction. Level shifters may cause area and Interconnect Length Overhead(ILO), and should be considered during floorplanning and post-floorplanning stages. In this paper, we propose a two phases framework VLSAF to solve voltage and level shifter assignment problem. At floorplanning phase, we use: a convex cost network flow algorithm to assign voltage; a minimum cost flow algorithm to assign level shifter. At post-floorplanning phase, a heuristic method is adopted to redistribute white spaces and calculate the positions and shapes of level shifters. Experimental results show VLSAF is effective
A New Buffer Planning Algorithm Based on Room Resizing
Abstract. This paper studies the buffer planning problem for interconnect centric floorplanning. Dead-spaces not held by blocks are the available location for buffer insertion. To make best use of these spaces for buffer requirements, we have to move blocks so that blocks' room size is adjusted and dead-spaces could be redistributed. In this paper, we introduce a new algorithm to move blocks not only within its room, but also in the space currently held by other blocks by pushing away these blocks if necessary without violating the topological and the total area. After applying this method of redistributing dead-spaces, the number of nets satisfying delay constraint can be optimized
Floorplanning and topology generation for application-specific Network-on-Chip
Abstract — Network-on-Chip(NoC) architectures have been proposed as a promising alternative to clas-sical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation prob-lem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Fi-nally, we allocate paths to minimize power consump-tion. The experimental results show our algorithm is effective for power saving. I
A novel fixed-outline floorplanner with zero deadspace for hierarchical design
ABSTRACT Fixed-outline floorplanning, which enables hierarchical design, is considered more and more important nowadays. In this paper, a novel SA-based Fixed-outline Floorplanner with the Optimal Area utilization named SAFFOA is introduced to improve the total wirelength. The basic idea is to build and solve a group of four quadratic equations in four variables iteratively, which can handle the fixed-outline constraint of any aspect ratio. A new topological representation called Ordered Quadtree is then custom-made for this basic idea to facilitate its integration into SA iterations. After the fixed-outline constraint with 100% area utilization is achieved, we will solve the tradeoff between the chip area and wirelength and thus concentrate on the latter in SA process. Experimental results show that the chip wirelength is decreased by about 16.8% and 8.6% on average, compared with two previous fixed-outline floorplanners on soft modules, which are both proved to be better than Parquet. Besides, our method is still competitive on the wirelength, even if compared with some leading-edge outline-free floorplanners. At last, Local Refinement is also adopted to guide the SA process and reshape soft modules to meet the constraint on their aspect ratios (ARs). With its help, SAFFOA can still generate feasible floorplans with no deadspace under a strict AR constraint such as 0.5, 2