Massive MIMO Systems With Low-Resolution ADCs: Baseband Energy Consumption vs. Symbol Detection Performance

In massive multiple-input multiple-output (MIMO) systems using a large number of antennas, it would be difficult to connect high-resolution analog-to-digital converters (ADCs) to each antenna component due to high cost and energy consumption problems. To resolve these issues, there has been much work on implementing symbol detectors and channel estimators using low-resolution ADCs for massive MIMO systems. Although it is intuitively true that using low-resolution ADCs makes it possible to save a large amount of energy consumption in massive MIMO systems, the relationship between energy consumption using low-resolution ADCs and detection performance has not been properly analyzed yet. In this paper, the tradeoff between different detectors and total baseband energy consumption including flexible ADCs is thoroughly analyzed taking the optimal fixed-point operations performed during the detection processes into account. In order to minimize the energy consumption for the given channel condition, the proposed scheme selects the best mode among various processing options while supporting the target frame error rate. The numerous case studies reveal that the proposed work remarkably saves the energy consumption of the massive MIMO processing compared with the existing schemes.11Ysciescopu

저지연 인체통신을 위한 동적 BCH 복호화 기법

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Cost-Efficient GPIP Processing for Large-Scale Multi-User MIMO Systems

This paper investigates a joint user selection, power allocation, and beamforming strategy for maximizing a weighted sum-spectral efficiency in a single-cell multi-user multiple-input multiple-output (MU-MIMO) system. Finding such a joint strategy is challenging due to the non-convexity of the sum-spectral efficiency function for the optimization variables. The recent algorithm, referred to as generalized power iteration precoding (GPIP), allows finding a stationary point in polynomial time for this non-convex problem. GPIP, however, is not scalable to a large-scale MU-MIMO system because of the overwhelming computational complexity. This high complexity makes the hardware energy efficiency worse as the number of antennas and users increases. This paper presents a low-cost simplified GPIP algorithm by jointly taking into account the implementation-level efficiency and algorithm-level performance. The proposed algorithm is to jointly harness the ideas of i) multiply-accumulate (MAC) operation reduction, ii) dynamic range reduction, and iii) low-complexity matrix inversion with approximate computing. Experimental results reveal that the proposed simplified GPIP algorithm reduces the total cost for solving the GPIP algorithm up to 99% while attaining a similar sum-spectral efficiency compared to that of a naive implementation method for GPIP in large-scale MU-MIMO systems

A 2.86Gb/s Fully-Flexible MU-MIMO Processor for Jointly Optimizing User Selection, Power Allocation, and Precoding in 28nm CMOS Technology

In 5G networks, as growing data usage exponentially, mobile operators need to increase network capacity. To increase the spectral efficiency of massive multiple-input multiple-output (MIMO) system, it is essential to enlarge the number of co-scheduled user equipments (UEs). As increasing the number of co-scheduled UEs up to the number of base station (BS) antennas, the conventional linear precoding schemes such as zero-forcing and maximum ratio transmission show poor capacity, as shown in Fig. 1. As a result, joint user selection, power allocation, and beamforming schemes, including the rank-adaptation zero-forcing (RA-ZF) and generalized power iteration precoding (GPIP) algorithms, are proposed for large-scale massive MIMO systems. However, the prior works on massive MIMO baseband architectures [1]-[4] are no longer suitable for these advanced algorithms; because they do not consider user selection or power allocation. Consequently, it is crucial to develop energy-and computationally efficient BS architecture that realizes the advanced algorithms to achieve a high spectral efficiency gain.1

Low-Complexity Voice Activity Detection Algorithm for Edge-Level Device

This paper presents two optimization techniques to relieve the computational complexity of the neural network based voice activity detection (VAD) task. Proposed techniques analyze the similarity between speech features by comparing the vectors at adjacent time steps and reduce the required computational cost by modifying internal elements based on the similarity. As a case study, a simple convolutional neural network for VAD was simulated with the proposed optimization techniques under the noisy environment, and experimental results show that the proposed techniques can reduce the required computational cost up to 33.6% with negligible performance degradation.2

Low-Latency Unfolded-KES Architecture for Emerging Storage Class Memories

This paper presents an advanced key-equation solver (KES) algorithm that can reduce the computing latency of BCH decoding for the high-speed storage class memory (SCM). Adopting the unfolding algorithm as a factor of two, compared to the conventional iterative KES scheme, the proposed work potentially halves the number of processing cycles for KES module, which is normally dominates the overall BCH decoding latency. In contrast that the straight-forward unfolding method increases the critical delay, we accelerate the major computing path that is activated at the most of SCM lifetime, preserving the critical delay of the proposed KES module as similar to that of the original one. When the minor cases are detected, the recovery processing is added at the end of the corresponding iteration. In order to reduce the additional energy consumption due to the unfolded architecture, we carefully deactivate the internal modules during the accelerated processing, which only necessitate for the recovery cycle. Implementation results show that the proposed KES architecture greatly reduces the decoding latency of arbitrary BCH decoder, leading to the high-speed and reliable emerging storages.11Nsciescopu

Hardware Analysis of Channel Estimation Method for IRS-Aided MIMO Wireless Systems

This paper presents hardware analysis of two practical channel estimation methods for intelligent reflecting surface (IRS)-aided communication systems. To evaluate the hardware costs, the number of required multiply-accumulation (MAC) operations of two practical channel estimation algorithms are analyzed. Regarding the hardware-level feasibility, dedicated channel estimation architecture is also implemented in 28-nm CMOS technology. Implementation results compare processing latency, area, and power consumption.2

저지연 IRS 통신을 위한 그룹 기반 위상 최적화 기법

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Energy-Efficient Precoding Architecture for Multi-User MIMO Systems

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A Study On Reliable High-Speed HBC Enhanced by ECC for Wearable Neural Interfaces

© 2022 IEEE.This work reports the first quantitative study about reliable high-speed human body communication (HBC) enhanced by error correction code (ECC) for wearable neural interfaces. For the first time, Bose-Chaudhuri-Hocqunghem (BCH) code was applied to the measured raw data of an HBC transceiver (TRX) that operated at about 100 Mb/s or faster to quantitatively assess the reliability improvement and the additional power and area cost associated with the BCH code. In our assessments, the (136, 128, 1) BCH code very efficiently improved the reliability of the HBC as it improved the eye height by up to about 95 % at costs of only 5-7% additional power and 46% additional silicon area. With slightly more power consumption up to 21% and 90% chip area, the (160, 128, 4) BCH code greatly improved the reliability of the HBC as it increased the eye height by up to 200%.1