Recent Progress with bioSFQ Circuit Family for Neuromorphic Computing

Superconductor single flux quantum (SFQ) technology is attractive for neuromorphic computing due to low energy dissipation and high, potentially up to 100 GHz, clock rates. We have recently suggested a new family of bioSFQ circuits (V.K. Semenov et al., IEEE TAS, vol. 32, no. 4, 1400105, 2022) where information is stored as a value of current in a superconducting loop and transferred as a rate of SFQ pulses propagating between the loops. This approach in the simplest case dealing with positive numbers, requires single-line transfer channels. In the more general case of bipolar numbers, it requires dual-rail transfer channels. For this need, a new comparator with dual-rail output has been developed and is presented. This comparator is an essential part of a bipolar multiplier that has also been designed, fabricated, and tested. We discuss strategic advantages of the suggested bioSFQ approach, e.g., an inherently asynchronous character of bioSFQ cells which do not require explicit clock signals. As a result, bioSFQ circuits are free of racing errors and tolerant to occasional collision of propagating SFQ pulses. This tolerance is due to stochastic nature of data signals generated by comparators operating within their gray zone. The circuits were fabricated in the eight-niobium-layer fabrication process SFQ5ee developed for superconductor electronics at MIT Lincoln Laboratory.Comment: 5 pages, 7 figures, 12 references. This paper was presented at Applied Superconductivity Conference, ASC 2022, October 23-28, 2022, Honolulu, Hawai

Diffusion stop-layers for superconducting integrated circuits and qubits with Nb-based Josephson junctions

New technology for superconductor integrated circuits has been developed and is presented. It employs diffusion stoplayers (DSLs) to protect Josephson junctions (JJs) from interlayer migration of impurities, improve JJ critical current (Ic) targeting and reproducibility, eliminate aging, and eliminate pattern-dependent effects in Ic and tunneling characteristics of Nb/Al/AlOx/Nb junctions in integrated circuits. The latter effects were recently found in Nb-based JJs integrated into multilayered digital circuits. E.g., it was found that Josephson critical current density (Jc) may depend on the JJ's environment, on the type and size of metal layers making contact to niobium base (BE) and counter electrodes (CE) of the junction, and also change with time. Such Jc variations within a circuit reduce circuit performance and yield, and restrict integration scale. This variability of JJs is explained as caused by hydrogen contamination of Nb layers during wafer processing, which changes the height and structural properties of AlOx tunnel barrier. Redistribution of hydrogen impurities between JJ electrodes and other circuit layers by diffusion along Nb wires and through contacts between layers causes long-term drift of Jc. At least two DSLs are required to completely protect JJs from impurity diffusion effects - right below the junction BE and right above the junction CE. The simplest and the most technologically convenient DSLs we have found are thin (from 3 nm to 10 nm) layers of Al. They were deposited in-situ under the BE layer, thus forming an Al/Nb/Al/AlOx/Nb penta-layer, and under the first wiring layer to junctions' CE, thus forming an Al/Nb wiring bi-layer. A significant improvement of Jc uniformity on 150-mm wafer has also been obtained along with large improvements in Jc targeting and run-to-run reproducibility.Comment: 7 pages, 9 figures; to be published in IEEE Transactions of Applied Superconductivit

Electrical stress effect on Josephson tunneling through ultrathin AlOx barrier in Nb/Al/AlOx/Nb junctions

The effect of dc electrical stress and breakdown on Josephson and quasiparticle tunneling in Nb/Al/AlOx/Nb junctions with ultrathin AlOx barriers typical for applications in superconductor digital electronics has been investigated. The junctions' conductance at room temperature and current-voltage (I-V) characteristics at 4.2 K have been measured after the consecutive stressing of the tunnel barrier at room temperature. Electrical stress was applied using current ramps with increasing amplitude ranging from 0 to ~1000 Ic corresponding to voltages across the barrier up to 0.65 V where Ic is the Josephson critical current. A very soft breakdown has been observed with polarity-dependent breakdown current (voltage). A dramatic increase in subgap conductance of the junctions, the appearance of subharmonic current steps, and gradual increase in both the critical and the excess currents as well as a decrease in the normal-state resistance have been observed. The observed changes in superconducting tunneling suggest a model in which a progressively increasing number of defects and associated additional conduction channels (superconducting quantum point contacts (SQPCs)) are induced by electric field in the tunnel barrier. By comparing the I-V characteristics of these conduction channels with the nonstationary theory of current transport in SQPCs based on multiple Andreev reflections by Averin and Bardas, the typical transparency D of the induced SQPCs was estimated as D ~ 0.7. The number of induced SQPCs was found to grow with voltage across the barrier as sinh(V/V_0) with V_0 = 0.045 V, in good agreement with the proposed model of defect formation by ion electromigration. The observed polarity dependence of the breakdown current (voltage) is also consistent with the model.Comment: 11 pages, 10 figure

Advanced Fabrication Processes for Superconducting Very Large Scale Integrated Circuits

We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating Single Flux Quantum(SFQ) digital circuits with very large scale integration on 200-mm wafers: the SFQ4ee and SFQ5ee nodes, where 'ee' denotes the process is tuned for energy efficient SFQ circuits. The former has eight superconducting layers with 0.5 {\mu}m minimum feature size and a 2 {\Omega}/sq Mo layer for circuit resistors. The latter has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm and a thin superconducting MoNx layer (Tc ~ 7.5 K) with high kinetic inductance (about 8 pH/sq) for forming compact inductors. A nonsuperconducting (Tc < 2 K) MoNx layer with lower nitrogen content is used for 6 {\Omega}/sq planar resistors for shunting and biasing of Josephson junctions. Another resistive layer is added to form interlayer, sandwich-type resistors of m{\Omega} range for releasing unwanted flux quanta from superconducting loops of logic cells. Both process nodes use Au/Pt/Ti contact metallization for chip packaging. The technology utilizes one layer of Nb/AlOx-Al/Nb JJs with critical current density, Jc of 100 {\mu}A/{\mu}m^2 and minimum diameter of 700 nm. Circuit patterns are defined by 248-nm photolithography and high density plasma etching. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO2 interlayer dielectric. The following results and topics are presented and discussed: the effect of surface topography under the JJs on the their properties and repeatability, critical current and Jc targeting, effect of hydrogen dissolved in Nb, MoNx properties for the resistor layer and for high kinetic inductance layer, technology of m{\Omega}-range resistors.Comment: 10 pages, 12 figures, 1 table, 27 references. The paper was presented on September 8, 2015 at the 12th European Conference on Applied Superconductivity, EUCAS 2015, 6-10 September 2015, Lyon, France, IEEE Transaction on Applied Superconductivity, 201