A novel highly adaptive routing for networks-on-chip

The degree of adaptiveness has a major impact on the performance of an adaptive routing method. This research work presents a novel turn model based routing method that provides a high degree of adaptiveness for 2D mesh. The result is that the proposed method reduces restrictions on the routing turns significantly and hence can provide path diversity using additional routes (both minimal and non-minimal). Experimental results show that the proposed method provides better performance (average latency and throughput) in comparison with the recent routing methods

A Fall and Near-Fall Assessment and Evaluation System

The FANFARE (Falls And Near Falls Assessment Research and Evaluation) project has developed a system to fulfill the need for a wearable device to collect data for fall and near-falls analysis. The system consists of a computer and a wireless sensor network to measure, display, and store fall related parameters such as postural activities and heart rate variability. Ease of use and low power are considered in the design. The system was built and tested successfully. Different machine learning algorithms were applied to the stored data for fall and near-fall evaluation. Results indicate that the Naïve Bayes algorithm is the best choice, due to its fast model building and high accuracy in fall detection

Efficient realization of parity prediction functions in FPGAs

In this paper, we propose an AND/XOR-based technology mapping method for efficient realization of parity prediction functions in field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, decomposing a circuit into sub-circuits with appropriate number of inputs can achieve an excellent implementation efficiency. Specifically, the proposed technology mapping method is based on Davio expansion theorem. The AND/XOR nature of the proposed method allows it to operate on XOR intensive circuits, such as parity prediction functions, efficiently. We conduct experiments using the parity prediction functions with respect to MCNC benchmark circuits. With the proposed approach, the number of configurable logic blocks (CLBs) is reduced by 67.6% (compared to speed-optimized results) and 57.7% (compared to area-optimized results), respectively. The total equivalent gate counts are reduced by 65.5%, maximum combinational path delay is reduced by 56.7%, and maximum net delay is reduced by 80.5% compared to conventional methods

A novel technology mapping method for AND/XOR expressions

In this paper, we propose a novel technology mapping technique for Look-Up Table (LUT) - based Field Programmable Gate Arrays (FPGA). The proposed technology mapping technique is based on AND/exclusive-OR (XOR) expressions. The AND/XOR nature of the proposed techniques can map many important XOR-intensive applications, such as error detecting/correcting, data encryption/decryption, and computer arithmetic circuits efficiently in FPGA. The typical EDA tools deal mainly with AND/OR expressions and therefore are quite inefficient for XOR-intensive applications. We design a new approach and conduct experiments using MCNC benchmark circuits in FPGA environment to demonstrate the effectiveness of our proposed technology mapping technique. The proposed technique is superior to the typical methods with respect to area. When using the proposed technique, the number of CLB is reduced by 67.6 % (speed-optimized one) and 57.7 % (area-optimised one) and the total number of equivalent gate counts is also reduced by 65.5 % compared to the typical methods