IEEE-1394 "Firewire" in der Bildverarbeitung

In diesem Beitrag wird gezeigt, daß der als IEEE 1394 "Firewire" bekannte Busstandard sehr gut für die Echtzeit-Datenübertragung in modernen Systemen zur Industriellen Bildverarbeitung geeignet ist. Ausgehend von einer Einführung in die Technologie wird ein allgemeines Systemkonzept beschrieben, auf dem mehrere industrielle Anwendungsbeispiele basieren, die ausführlich dargestellt werden

Minimal routing in reconfigurable communication networks

The data throughput of communication networks of MIMD computers increases if only local communication can be achieved. Hence, adapting the network topology to the application and using a flexible routing algorithm promises improved performance. Different routing algorithms for ATM-networks and MIMD computers have been investigated. In result a topology-independent routing criterion has been found and implemented into a minimal routing algorithm. The routing problem is split into a topology-dependent addressing problem, which needs to be solved once for every topology, and into a topology-independent evaluation of addresses allowing a direct VLSI-implementation. Experiments demonstrate the applicability of the routing algorithm to topologies of varying connectivity and regularity and different buffering styles

Consumer networking infrastructure based on IEEE 1394b

This paper presents a consumer networking infrastructure for all digital data transport within a home. IEEE 1394b provides a unified high performance serial bus for communication, multimedia, and home automation use. Other in-house or external communication technologies can be connected via gateways

Near-Optimal Scheduling of Synchronous Data-Flow Graphs by Exact Calculation of Inter-Processor Communication Costs

; p j ) the earliest time, when all input data for vertex v i are available at processor p j . The algorithm assigns v i to the processor p j that maximises DL. In (1) DA(v i ; p j ) characterizes interprocessor communication cost and represents the earliest possible time to start the computation of v i with respect to communication. The common estimation which will be used as reference assumes that the difference between DA(v i ; p j ) and the time when all ancestor tasks of v i are finished is equal to the maximal product of the amount of data to be transferred and the number of hops between the two communicating processors. This approach will be compared to the exact calculation of interprocessor communication costs by software ro

Modern electronic technologies in production of photo cameras

The contribution demonstrates the co-operation of electronic, mechanical and optical components and units, controlled by the necessary software, in a modern color scanner. This equipment offers a solution in the mind of the radical changes of the world of photography: images will not be captured on celluloid as now, but be acquired as data by photosensitive chips, as in digital cameras and scanners. The equipment which is currently available, is a color photo scanner that combines the capabilities of a camera and a scanner. This equipment captures the image of any three-dimensional object and allows to process the result immediately on a computer. Pictures can be taken from any static object, whereby a color sensitive CCD line sensor moved by a highly accurate operating step motor scans the object and registers its color composition, shape and size

A parallel neural network emulator based on application-specific VLSI communication chips

This work describes a parallel neural network emulator which combines use of application-specific VLSI communication processors and standard DSPs as programmable processing elements. Locally interconnected communication processors attached to each DSP can span up 2D- or 3D-grids containing large number of computing nodes and thus form highly parallel multiprocessor networks capable of global pipelined packet switched routing. The use of standard DPSs as processing element enables the emulation of different types of neurons. These include biologically inspired models with learnable synaptic weights and delays, variable neuron gain, and static and dynamic thresholding. We describe applications of the emulator that include neural robot control as well as temporal signal processing, e. g. beamforming

A parallel DSP-based neural network emulator with CMOS VLSI paket switching hardware.

This work describes a parallel neural network emulator which uses standard DSPs and application-specific VLSI communication processors with an integrated hardware routing algorithm. The use of DSPs as programmable processing elements enables the emulation of different types of neurons including biologically inspired models with learnable synaptic weights and delays, variable neuron gain, and static and dynamic thresholding. Locally interconnected communication processors attached to each DSP can span up a 2D- or 3D-computing grid and thus form a highly parallel network topology capable of global packet switching routing

Flaechiger Roentgendetektor

DE 102005012443 A1 UPAB: 20061109 NOVELTY - The detector has a photo diode arrangement with a lateral unstructured photodiode layer (3), and two electrodes (4, 5) arranged on both sides of the layer. The photodiode layer is formed as P-i-N photodiode layer. A scintillator layer (6) extends over the diode arrangement and arranged on one of the two electrodes. A laser beam source with a deflecting unit is provided for selectively photo excitation of the photodiode layer. USE - Used in medicine in a picture-giving diagnostic e.g. radiological diagnostic such as x-ray and mammography, surgery and radiotherapy. ADVANTAGE - The configuration of the x-ray detector facilitates the manufacture of the detector in a cost-effective manner with low technological expenditure