Software detection mechanisms providing full coverage against single bit-flip faults

Increasing design complexity for current and future generations of microelectronic technologies leads to an increased sensitivity to transient bit-flip errors. These errors can cause unpredictable behaviors and corrupt data integrity and system availability. This work proposes new solutions to detect all classes of faults, including those that escape conventional software detection mechanisms, allowing full protection against transient bit-flip errors. The proposed solutions, particularly well suited for low-cost safety-critical microprocessor-based applications, have been validated through exhaustive fault injection experiments performed on a set of real and synthetic benchmark programs. The fault model taken into consideration was single bit-flip errors corrupting memory cells accessible to the user by means of the processor instruction set. The obtained results demonstrate the effectiveness of the proposed solutions

SIED: software implemented error detection

This paper presents a new error detection technique called software implemented error detection (SIED). The proposed method is based on a new control check flow scheme combined with software redundancy. The distinctive advantage of the SIED approach over other fault tolerance techniques is the fault coverage. SIED is able to cope with faults affecting data and the program control flow. By-applying the proposed approach on several benchmark programs, we evaluate the error detection capabilities by means of several fault injection experiments. Experimental results underline very good error detection capabilities for the obtained hardened version of selected benchmark programs

Performance evaluation and failure rate prediction for the soft implemented error detection technique

This paper presents two error models to evaluate safety of a software error detection method. The proposed models analyze the impact on program overhead in terms of memory code area and increased execution time when the studied error detection technique is applied. For faults affecting the processor's registers, analytic formulas are derived to estimate the failure rate before program execution. These formulas are based on probabilistic methods and use statistics of the program, which are collected during compilation. The studied error detection technique was applied to several benchmark programs and then program overhead and failure rate was estimated. Experimental results validate the estimated performances and show the effectiveness of the proposed evaluation formulas

Performance evaluation and failure prediction for the soft implemented error detection technique

International audienceThis paper presents two error models to evaluate safety of a software error detection method. The proposed models analyze the impact on program overhead in terms of memory code area and increased execution time when the studied error dectection technique is applied. For faults affecting the processors registers, analytic formulas are derived to estimate the failure rate before program execution. These formulas are based on probabilistic methods and use statistics of the program, which are collected during compilation. The studied error detection technique was applied to several benchmark programs and then program overhead and failure rate was estimated. Experimental results validate the estimated performances and show the effectiveness of the proposed evaluation formulas

Evaluation of a software-based error detection technique by RT-level fault injection

International audienceThis paper discusses the efficiency of a software hardening technique when transient faults occur in the processor elements. Faults are injected in the RT-Level model of the processor, thus providing a more comprehensive view of the robustness compared with injections limited to the registers in the programmer model (e.g. injections based on an Instruction Set Simulator or using instructions of the processor to modify contents of registers)

Efficiency of transient bit-flips detection by software means: a complete study

International audienceThis-paper characterizes the effectiveness of an error detection technique that addresses transient faults induced by the environment (radiation, EMC) in processor-based architectures. Experimental results obtained from fault injection sessions performed on two platforms built around a 32-bit digital signal processor and an 8-bit microcontroller, provide objective figures about the efficiency of the proposed approach

Validation by fault injection of a software error detection technique dealing with critical Single Event Upsets

International audienceSingle Event Upset (SEU) phenomena is becoming a major concern in applications design, especially in the context of space applications. In this paper, a software error detection methodology is evaluated by means of fault injection performed on a 64-bits processor while it executes a benchmark application. The obtained results demonstrate the effectiveness of the proposed methodology: a high percent of faults affecting the program counter of the studied processor were detected

On the Use of Model Checking for the Verification of a Dynamic Signature Monitoring Approach

International audienceConsequences of transient faults represent a significant problem for today's electronic circuits and systems. As the probability of such errors increases, incorporation of error detection and correction mechanisms is mandatory. It is well known that traditional techniques that validate system's reliability do not cover the whole spectrum of fault scenarios, because fault models are linked to target architectures. Therefore, validating the completeness of robust fault tolerance techniques is a major issue when assessing reliability improvements these techniques can produce. In this paper, we propose an original approach to evaluate the system reliability with respect to Single Event Upset (SEU) errors. It is based on model-checking principles. In addition, a signature analysis technique is evaluated. This technique was previously validated using a simulation-based fault injection approach. Simulation results showed that no error escapes detection. However, simulation based fault injection cannot guarantee that all fault consequences have been investigated. This limitation motivates us to explore a formal verification approach that targets a complete validation. Model checking has a fundamental advantage over classic fault-injection techniques: it can cover all possible SEU fault scenarios from a predefined class. Results reported in this paper demonstrate the efficiency of this validation approach over usual simulation-based techniques

Validating a dynamic signature monitoring approach using the LTL model checking technique

International audienceConsequences of transient errors represent a significant problem for todays electronic circuits and systems. As the probability of such errors increases, incorporation of error detection and correction mechanisms is a major concern. This represents one of the major industry focuses. An important challenge is that traditional validation techniques do not cover the whole spectrum of single bit-flip fault scenarios. In this paper, a new signature analysis method is proposed. This technique was previously validated using simulation-based fault injection. This validation showed that no errors escape detection. In addition, we explore a verification approach based on model-checking targeting complete validation. It presents a fundamental advantage over classic fault-injection techniques: it covers all possible single bit-flip fault scenarios. Experimental results illustrate the effeciency of this validation approach over usual simulation-based techniques