Techniques and circuits for ultra-efficient energy harvesting sensor nodes

Sensor nodes play increasingly important role in various enterprises like agriculture, transport, defence etc. As the number of sensor nodes increase, their energy consumption, running and maintenance costs become detrimental to their implementation. Energy harvesting is an alternative to tethered or battery-powered sensor nodes which holds the promise of long-term sustainable operation. The energy available however, is limited and decreases further as sensor nodes become smaller. A small size also calls for tighter and possibly, monolithic integration. The limited available energy and small form-factor necessitates high energy efficiency in sensor nodes that must be guaranteed at design time. While integrated circuit (IC) design uses well-characterized device models for simulation, energy harvesters rarely have accurate models upon which to draw for circuit design. This research explores development of models for small cm2 photovoltaic cells by first characterizing them in real-world conditions and develop simulation models to enable IC design. The models are then used to investigate power conversion circuits and techniques for improving energy efficiency of sensor nodes. In this thesis, a compact and low-cost characterization scheme is used to develop a simulation model for photovoltaic cell which shows good correlation with measurements. The results of this work show the potential to improve sensor node design margining by as much as 16×. Holistic system solutions are then explored to maximize utilization of harvested energy with efficient power conversion resulting in a 30% increase in computation cycles in the sensor node. Ultra-low-power rail monitor and oscillator circuits are also presented. The rail monitor exploits state-awareness to provide the best-reported balance in response speed and power consumption. The oscillator uses sub-cycle comparator duty-cycling to provide the lowest energy per cycle in the smallest area while exhibiting comparable line and temperature sensitivities. This research has resulted two journals, three peerreviewed conference papers and three granted patent

Integrated reciprocal conversion with selective direct operation for energy harvesting Systems - data

Data for plots in the paper Savanth, P. A. K., Weddell, A., Myers, J., Flynn, D. &amp; Al-Hashimi, B. 14 Jun 2017 In : IEEE Transactions on Circuits and Systems I: Regular Papers. p. 1-10 in Comma Separated Values CSV format along with a Readme file for description of each file.</span

Dataset supporting: A sub-nW/kHz Relaxation Oscillator with Ratioed Reference and sub-Clock Power Gated Comparator

Measured data for results presented in the paper: &quot;A sub-nW/kHz Relaxation Oscillator with Ratioed Reference and sub-Clock Power Gated Comparator&quot; to be published in Journal of Solid State Circuits (JSSC) authored by Anand Savanth, Alex S. Weddell, James Myers, David Flynn and Bashir M. Al-Hashimi</span

Integrated reciprocal conversion with selective direct operation for energy harvesting systems

Energy harvesting IoT systems aim for energy neutrality, i.e. harvesting at least as much energy as is needed. This however, is complicated by variations in environmental energy and application demands. Conventional systems use separate power converters to interface between the harvester and storage, and then to the CPU system. Reciprocal power conversion has recently been proposed to perform both roles, eliminating redundancy and minimizing losses. This paper proposes to enhance this topology with ‘selective direct operation’, which completely bypasses the converter when appropriate. The integrated system, with 82% bidirectional conversion efficiency, was validated in 65nm CMOS with only the harvester, battery and decoupling capacitors being off-chip. Optimized for operation with cm² photo-voltaic cell and a 32-bit sub-threshold processor, the scheme enables up to 16% otherwise wasted energy to be utilized to provide &gt;30% additional compute cycles under realistic indoor lighting conditions. Measured results show 84% peak conversion efficiency and energy neutral execution of benchmark sensor software (ULPBench) with cold-start capability

Energy neutral sensor system with micro-scale photovoltaic and thermoelectric energy harvesting

Minimizing power conversion losses is critical for energy neutral operation of micro-scale energy harvested sensor nodes. These small form-factor sensor nodes rely on miniature harvesters with low output voltages that must be boosted with large conversion ratios to recharge batteries or super-capacitors. Selective Direct Operation (SDO), a technique to selectively avoid power conversion and thereby eliminate conversion loss in energy harvested systems has been demonstrated as an effective technique for light harvesters. This paper extends SDO to thermoelectric generators (TEGs). SDO exploits the ultra-low circuit functional voltages, enabling sensor systems to effectively harvest energy from cm-scale TEGs which output few 10's of mW but at low output voltages (100's of mV). PV cell construction from prior-work, TEG characterization and field measurements are presented in this paper to demonstrate the effectiveness of SDO and co-designing energy harvesters, power conversion circuits and digital sub-systems

Evaluation and analysis of single-phase clock flip-flops for NTV applications

Performance slack in IoT applications is routinely exploited in sensor nodes to minimize power by aggressive voltage scaling. However, scaling voltage to sub-threshold levels causes severe degradation in performance and is prone to On Chip Variation (OCV). In contrast, Near Threshold Voltage (NTV) operation offers a good balance between performance loss, OCV and energy reduction and is promising for industry adoption. Unlike sub-threshold operation, where leakage power dominates, NTV designs benefit from dynamic power saving techniques, such as Single-Phase Clocked Flip-Flops (SPC FFs), which eliminate internal clock buffers. In this context, this work reviews prominent types of state-of-the-art SPC FFs and analyses their suitability for NTV operation. Five SPC FFs are reviewed and based on a preliminary analysis, two designs, which meet all NTV circuit design requirements are further investigated. These SPC FFs are designed for NTV operation in TSMC 65LP and compared against the classic transmission gate FF (TGFF). Celllevel design issues and variation are explored in the context of a 5000 gate AES encryption macro. Key design issues are identified, which erode the claimed benefits of SPC FFs when implemented as part of a larger design. We conclude that aggressive reduction in FF clock loading offers benefits but can lead to functional failures when OCV is considered, especially at NTV. Given the theoretical benefits of SPC FFs for enabling IoT, the need for further work on SPC FF designs is highlighted

Dataset for &#39;Ultra-Low Power 18-Transistor Fully-Static Contention-Free Single-Phase Clocked Flip-Flop in 65nm CMOS&#39;

This dataset supports the article entitled &quot;Ultra-Low Power 18-Transistor Fully-Static Contention-Free Single-Phase Clocked Flip-Flop in 65nm CMOS&quot; accepted for publication in IEEE Journal of Solid State Circuits, October 2018</span