Hybrid resonant -clocked digital design.

Diminishing voltage scaling trends in modern process technology have resulted in the increased importance of low-energy design in mobile, battery-operated systems and wall-powered server applications alike. This dissertation describes high-performance dynamic circuitry and clock methodologies that rely on charge recovery to return energy to the power source, thereby reducing dynamic power dissipation. Specifically, we propose a novel hybrid adiabatic logic family, called Boost Logic, which achieves high-efficiency and high-performance operation through a combination of conventional and charge-recovery structures. A Boost Logic test chip has been fabricated in a 0.13mum CMOS process with on-chip inductors. This test chip demonstrates 60% energy efficiency, while running at 1.3GHz, the highest clock frequency achieved for adiabatic logic to date. We also propose a novel latch-based design methodology for resonant-clocked pipelines, which provides substantial energy savings over conventional CMOS implementations without affecting the throughput or latency of the design. Our proposed methodology enables the fully-automated resonant-clocked implementation of any latch-based digital circuit. Furthermore, we propose a static-timing analysis framework that facilitates such an automated design flow. Relying on the proposed methodology, we have designed and fabricated two test chips, called RF1 and RF2, using a 0.13mum CMOS process with integrated inductors. RP is a 0.8-1.2GHz frequency-tunable FIR filter which operates using a single clock phase and achieves 76% clock power reduction over conventional fCV2 dissipation. RF2 is a 1GHz FIR filter featuring a distributed self-resonant clock generator which achieves 84% clock power reduction over conventional fCV2f. At 133MHz/Tap/inBits/coeffBits, RF2 achieves the lowest FIR filter metric published to date.Ph.D.Applied SciencesElectrical engineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/126814/2/3276286.pd

Resonant System Design with Coarse Grained Pipelines

In this report, we present an efficient approach to resonant system design. Our approach involves the use of resonant clocks to drive level sensitive latches in pipelined datapaths. Through judicious design of these timing elements, the energy efficiency of resonant clocking can be obtained without performance penalties, while maintaining robust, race-free operation. Since our approach involves driving only the timing elements with resonant clocks and places no restrictions on the type of computational logic, the method can be used with existing static CMOS design flows. We describe our technique for two, three and four phase clock systems and present clock generation mechanisms. We also introduce the level-sensitive timing elements to be used with these clocks and discuss how they are introduced into a datapath.

Boost Logic: A High Speed Energy Recovery Circuit Family

In this paper, we propose Boost Logic, a logic family which relies on voltage scaling, gate overdrive and energy recovery techniques to achieve high energy efficiency at frequencies in the GHz range. The key feature of our design is the use of an energy recovering “boost ” stage to provide an efficient gate overdrive to a highly voltage scaled logic at near threshold supply voltage. We have evaluated our logic family using post-layout simulation of an 8-bit pipelined array multiplier in a ¢¤£¦¥¨§� © m CMOS process with ���� � =340mV. At 1.6GHz and a 1.3V supply voltage, the Boost multiplier dissipates 8.11pJ per computation. Comparing results from post-layout simulations of boost and voltage-scaled conventional multipliers, our proposed logic achieves 68 % energy savings with respect to static CMOS. Using low � �� � devices, Boost Logic has been verified to operate at 2GHz with a 1.25V voltage supply and 8.5pJ energy dissipation per cycle.

A 225 MHz resonant clocked ASIC chip

We have recently designed, fabricated, and successfully tested an experimental chip that validates a novel method for reducing clock dissipation through energy recovery. Our approach includes a single-phase sinusoidal clock signal, an L-C resonant sinusoidal clock generator, and an energy recovering flip-flop. Our chip comprises a dual-mode ASIC with two independent clock systems, one conven-tional and one energy recovering, and was fabricated in a 0.25µm bulk CMOS process. The ASIC computes a pipelined discrete wavelet transform with self-test and contains over 3500 gates. We have verified correct functionality and obtained power measure-ments in both modes of operation for frequencies up to 225MHz. In the energy recovering mode, our power measurements account for all of the dissipation factors, including the operation of the in-tegrated resonant clock generator, and show a net energy savings over the conventional mode of operation. For example, at 115MHz, measured dissipation is between 60 % and 75 % of the conventional mode, depending on primary input activity. To our knowledge, this is the first ever published account of a direct experimentally-measured comparison between a complete energy recovering ASIC chip and its conventional implementation correctly operating in sil-icon at frequencies exceeding 100MHz