Combinational Circuit Optimization

Introduction Low power VLSI design can be achieved at various levels of the design abstraction from algorithmic and system levels down to layout and circuit levels (see Figure 1). Power optimization techniques at the system, architectural (behavioral) design level, register-transfer (RT) level, physical design level, and the circuit level have been addressed by researchers in the past. Logic synthesis however, is an important part of the design cycle for a digital system. This means that in order to minimize power effectively, power has to be considered during logic synthesis and optimization. Logic synthesis provides the automatic synthesis of gate-level netlists, minimizing some objective function subject to various constraints. The goal, in general is to obtain a minimum area circuit subject to a given delay requirement. Example inputs to a logic synthesis system include two-level logic representation, multi-level Boolean networks, finite state machines and technology mapped circ