Improving Energy Usage in Energy Harvesting Wireless Sensor Nodes Using Weather Forecast

Battery powered wireless sensor nodes are used in many applications. They can be placed in remote locations and can operate for a long period of time without the need for maintenance. However, finite battery lifetime is one of the main limitations of such devices. Energy harvesting can be used to recharge batteries from environmental energy sources. This enables continuous work when energy neutrality is satisfied. For optimal use of available energy, when energy harvesting is used, the optimization goal switches from energy management to workload maximization while maintaining energy neutrality. In order to achieve energy neutrality, prediction of energy that can be harvested in the future is needed. This prediction can be based on previous measured data. However, this approach can be unreliable when weather conditions change during the day or between days. To improve prediction precision, weather forecast can be used. This information has been used to predict energy that can be harvested in the future but only for the next few hours. We present a two-level predictor that uses cloud cover information from hourly weather forecast for next 24 hour period to predict energy that can be harvested in the same time interval. Proposed predictor achieves a 26% less prediction mean absolute percentage error, a 15% less mean absolute deviation percent error and allows an 8% better performance of simulated wireless sensor node compared to Exponentially Weighted Moving Average (EWMA) predictor

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Selective flexibility: Breaking the rigidity of datapath merging

Hardware specialization is often the key to efficiency for programmable embedded systems, but comes at the expense of flexibility. This paper combines flexibility and efficiency in the design and synthesis of domain-specific datapaths. We merge all individual paths from the Data Flow Graphs (DFGs) of the target applications, leading to a minimal set of required resources; this set is organized into a column of physical operators and cloned, thus generating a domain-specific rectangular lattice. A bus-based FPGA-style interconnection network is then generated and dimensioned to meet the needs of the applications. Our results demonstrate that the lattice has good flexibility: DFGs that were not used as part of the datapath creation phase can be mapped onto it with high probability. Compared to an ASIC design of a single DFG, the speed of our domain-specific coarse-grained reconfigurable datapath is degraded by a factor up to 2x, compared to 3-4x for an FPGA; similarly, our lattice is up to 10x larger than an ASIC, compared to 20-40x for an FPGA. We estimate that our array is up to 6x larger than an ASIC accelerator, which is synthesized using datapath merging and has limited or null generality. © 2012 EDAA