Design of a control architecture for an underwater remotely operated vehicle (ROV) used for search and rescue operations

summary:A control system architecture design for an underwater ROV, primarily Class I - Pure Observation underwater ROV is presented in this paper. A non-linear plant model was designed using SolidWorks 3D modeling tool and is imported to MATLAB as a 3D model. The non-linear modeled plant is linearized using the MATLAB linear analysis toolbox to have a linear approximate model of the system. The authors designed controllers for the linear plant model of underwater ROV. PID controllers are utilized as a controller of the modeled plant. The PID tuning tools by MATLAB are utilized to tune the controller of the plant model of underwater ROV. The researchers test the control design of underwater ROV using MATLAB Simulink by analyzing the response of the system and troubleshoot the control design to achieve the objective parameters for the control design of underwater ROV

Design and Implementation of A Power Effective Digital Logic Accelerator and Ultra-Low Power SRAMs for AI Edge Applications

Edge computing is gaining more and more attention along the with the increasing popularity of artificial intelligence systems. Since the data is being readily available, AI applications are often required to have the results in nearly real time too. One example of an edge computing platform is an object detection system that is deployed in an autonomous underwater vehicle (AUV). A power effective digital logic accelerator (DLA) with output reuse, hardware padding, and a new reshape module is demonstrated in Chapter 2. Measurement on a silicon shows a low power consumption of the design. It has a performance of 40.96 GOPS operating at a power of 196.8 mW which is almost 19 times lower than the FPGA counter part. It is implemented using the TSMC 180-nm CMOS process, where the chip area is 53.63 mm2. The area and power efficiencies are 0.7638 GOPS/mm2 and 0.2081 TOPS/W, respectively. A figure of merit (FOM) based on the performance and power shows that the proposed design is the best so far. Although the DLA in Chapter 2 shows a low power performance, the power effectiveness needs to be improved. Experiments show that majority or the energy of the DLA is consumed by the SRAMs thereof. Hence, two ultra-low power SRAM designs are demonstrated in Chapters 3 and 4, respectively. In Chapter 3, a single-ended SRAM cell design is demonstrated. It uses a power gating mechanism to reduce power consumption while a power-delay product (PDP) reduction circuit is added to compensate for speed loss. One issue caused by the single-ended design is poor noise performance. In Chapter 4, a novel asymmetrical Schmitt-trigger based SRAM cell is presented. It showed an improved static noise margin and not sacrificing performance. Measurements show an ultra-low power consumption of 6.8 fJ and 4.23 fJ per bit for the single-ended SRAM and Schmitt-trigger SRAM, respectively. An FOM based on the energy per bit and supply voltage is used to compare the SRAM designs to many prior SRAMs in the last decade. Finally, the dissertation is concluded in Chapter 5 and the future of this work is also discussed