Diagrammes de Décision de Données pour l'analyse de systèmes ProMeLa

In this paper, we show how to verify CTL properties, using symbolic methods, on systems written inProMeLa. Symbolic representation is based on Data Decision Diagrams (DDDs) which are n-valued DAGs designed to represent dynamic systems with integer domain variables. We describe principal components used for the verification of ProMeLa systems (DDD, representation of ProMeLa programs with DDD, the transposition of the execution of ProMeLa instructions into DDD). Then we compare and contrast our method with the model checker SPIN or classical BDD techniques, to highlight what system classes whether SPIN or our tool is more relevant for.Cet article montre comment vérifier des propriétés CTL sur des systèmes décrits en ProMeLa en utilisant des méthodes symboliques. On a choisi les Diagrammes de Décision de Données (DDD) comme type de données abstrait. Il s'agit d'arbres n-aires permettant de représenter des systèmes dynamiques articulant des variables entières. On décrit les principaux composant utilisés pour la vérification de systèmes ProMeLa (DDD, représentation du système ProMeLa et la transposition de ses instructions sur les DDD). Puis nous comparons notre méthode avec le Model-Checker SPIN et les techniques classiques utilisant les BDD afin de déterminer quelles sont les classes de systèmes pour lesquelles notre méthode s'avère le plus efficace

Data Decision Diagrams for Promela Systems Analysis

International audienceIn this paper, we show how to verify computation tree logic (CTL) properties, using symbolic methods, on systems described in Promela. Symbolic representation is based on data decision diagrams (DDDs) which are n-valued Shared Decision Trees designed to represent dynamic systems with integer domain variables. We describe principal components used for the verification of Promela systems (DDD, representation of Promela programs with DDD, the transposition of the execution of Promela instructions into DDD). Then we compare and contrast our method with the model checker SPIN or classical binary decision diagram (BDD) techniques to highlight as to which system classes SPIN or our tool is more relevant

A Lightweight Southbound Interface for Standalone P4-NetFPGA SmartNICs

International audienceWe present a lightweight Southbound Interface (SBI) for P4→NetFPGA devices, aimed at enhancing the capability of NetFPGA Smart Network Interface Cards (SmartNICs) to work in standalone mode. We propose a custom protocol allowing the control plane to remotely populate the board's routing tables and query runtime information. We achieve this thanks to the implementation of a lookup table (LUT) extern function that can be directly edited by the P4 program-a feature notably lacking in the context of P4→NetFPGA

Diagrammes de Décision de Données pour l'analyse de systèmes ProMeLa

In this paper, we show how to verify CTL properties, using symbolic methods, on systems written inProMeLa. Symbolic representation is based on Data Decision Diagrams (DDDs) which are n-valued DAGs designed to represent dynamic systems with integer domain variables. We describe principal components used for the verification of ProMeLa systems (DDD, representation of ProMeLa programs with DDD, the transposition of the execution of ProMeLa instructions into DDD). Then we compare and contrast our method with the model checker SPIN or classical BDD techniques, to highlight what system classes whether SPIN or our tool is more relevant for.Cet article montre comment vérifier des propriétés CTL sur des systèmes décrits en ProMeLa en utilisant des méthodes symboliques. On a choisi les Diagrammes de Décision de Données (DDD) comme type de données abstrait. Il s'agit d'arbres n-aires permettant de représenter des systèmes dynamiques articulant des variables entières. On décrit les principaux composant utilisés pour la vérification de systèmes ProMeLa (DDD, représentation du système ProMeLa et la transposition de ses instructions sur les DDD). Puis nous comparons notre méthode avec le Model-Checker SPIN et les techniques classiques utilisant les BDD afin de déterminer quelles sont les classes de systèmes pour lesquelles notre méthode s'avère le plus efficace

A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip

6 pagesInternational audienceIn this paper we present a reconfigurable routing algorithm for a 2D-Mesh Network-on-Chip (NoC) dedicated to fault-tolerant, Massively Parallel Multi-Processors Systems on Chip (MP2-SoC). The routing algorithm can be dynamically reconfigured, to adapt to the modification of the micro-network topology caused by a faulty router. This algorithm has been implemented in a reconfigurable version of the DSPIN micro-network, and evaluated from the point of view of performance (penalty on the network saturation threshold), and cost (extra silicon area occupied by the reconfigurable version of the router)

A polynomial algorithm to prove deadlock-freeness of wormhole networks

International audienceDeadlocks are an important issue in wormhole networks and a lot of works have been done on deadlock avoidance. Sufficient and necessary deadlock-freeness conditions have been proposed and used to build deadlock-free wormhole networks. But none of these works provide an efficient way to verify if a given network is deadlock-free. The present article proposes a new sufficient and necessary condition associated with a polynomial algorithm to check if a given network is deadlock-free. This new algorithm identifies escape paths from channels that are involved in circular dependencies. Identifying escape paths can be easily done by studying strongly connected components of the dependency graph instead of studying individually each cycle. The proposed algorithm has been implemented in a tool for automatic detection of deadlocks in wormhole networks (ODI). ODI has been used to establish the deadlock-freeness of complex realistic networks and networks with defective routers

A Tool for Automatic Detection of Deadlock in Wormhole Networks on Chip

International audienceWe present an extension of Duato's necessary and sufficient condition a routing function must satisfy in order to be deadlock-free, to support environment constraints inducing extra-dependencies between messages. We also present an original algorithm to automatically check the deadlock-freeness of a network with a given routing function. A prototype tool has been developed and automatic deadlock checking of large scale networks with various routing functions have been successfully achieved