INTEGRATING UAHPL-DA SYSTEMS WITH VLSI DESIGN TOOLS TO SUPPORT VLSI DA COURSES

Because of rapid growth in areas related to digital design automation (DA) of very large scale integration (VLSI) systems, it has become necessary to introduce related courses into the university curriculum. In order to support effective teaching and laboratory courses, it is essential to have a complete operational environment established with the help of state-of the-art tools. In this paper, we explain the establishment of such an environment, which is accomplished with the integration of two systems: 1) a DA system which automatically produces VLSI layouts of digital systems modeled in Universal Hardware Programming Language (UAHPL); and 2) a set of VLSI tools, which in addition to several other functions can be used for simulation and verification of layout designs. Compared with other approaches, the integrated DA system provides a very simple user interface, fast turnaround time, no restriction on the final structure of the layout, and simulation and verification of all phases of design. The new environment, called UAHPL-based VLSI DA, is excellent for teaching and research at universities

Fuzzy Simulated Evolution Algorithm for Topology Design on Campus Networks

The topology design of campus networks is a hard contrained combinatorial optimization problem. It consists of deciding the number, type, and location of the active network elements (nodes) and links. This choice is dictated by physical and technological constraints and must optimize several objectives. Example of objectives are monetary cost, network delay, and hop count between communicating pairs. Furthermore, due to the nondeterministic nature of network traffic and other design parameters, the objectives criteria are imprecise. Fuzzy logic provides a suitable mathematical framework in such a situation. In this paper, we present an approach based on Simulated Evolution algorithm for the design of campus network topology. The two main phases of the algorithm, namely evaluation and allocation, have been fuzzified. To diversify the search, we have also incorporated Tabu Search-based characteristics in the allocation phase of the SE algorithm. This approach is then compared with Simulated Anealing algorithm, which is another well-known heuristic. Results show that on all test cases, Simulated Evolution algorithm more intelligent search of the solutions subspace and was able to find better solutions than Simulated Anealing

Area-Time Optimal Adder with Relative Placement Generator

This paper presents the design of a generator, for the production of area-time-optimal adders. A unique feature of this generator is that, it integrates synthesis and layout by providing relative placement information.. Relative placement information provides better support for structured layout and easier integration flow with data-path placer. Adders generated using the proposed generator are dynamically configured for a given technology library, wire-load model, delay, and area goal. Adders of sizes 1 to 1024 bits are produced. The adder architecture used in this generator is a hybrid of Brent & Kung, carry select, and ripple carry adders. When compared with Synopsys’ fast adders, a 20- 50% reduction in area with comparable delays are produced. This generator has been integrated into Synopsys high-performance datapath design tool Module Compiler

Area-Time Optimal Adder with Relative Placement Generator

This paper presents the design of a generator, for the production of area-time-optimal adders. A unique feature of this generator is that, it integrates synthesis and layout by providing relative placement information.. Relative placement information provides better support for structured layout and easier integration flow with data-path placer. Adders generated using the proposed generator are dynamically configured for a given technology library, wire-load model, delay, and area goal. Adders of sizes 1 to 1024 bits are produced. The adder architecture used in this generator is a hybrid of Brent & Kung, carry select, and ripple carry adders. When compared with Synopsys’ fast adders, a 20- 50% reduction in area with comparable delays are produced. This generator has been integrated into Synopsys high-performance datapath design tool Module Compiler

WWW & E-Commerce

Topics Covered in this Session l A brief overview of relevant Internet Services l Web and HTML l Client/Server Software and HTTP l Images, Frames, Forms & Web-DB l E-Commerce l Several other related topic