BEHAVIOURAL MODELLING FOR THE DESIGN OF HIGH SPEED PHYSICAL LAYERS

This thesis work is the result of a 9 months activity at the IP&Reuse Division - Physical Layer team - of Intel Mobile Communications GmbH in Munich, Germany; the work has been sponsored by the company itself and by an Erasmus grant in the context of ‘LifeLongLearning Program’, academic year 2011-2012. It has been developed a high-level simulation environment to support the concept, architectural exploration and system-level performance analysis of High Speed Serial Interfaces’ Physical Layer. Equivalent representation using Analogue Mixed Signal - Hardware Description Languages (HDLs-AMS) have been also implemented to speed-up full chip transistor-level transient simulations. In Chapter 1 is presented an overview of the state of the art on methodologies, styles, implementation languages and simulation tools used in the design of mixed-signal systems and in the creation of behavioural models. Practical rules for trading off accuracy and speed are also discussed. In Chapter 2, a high-level description of a generic Physical Layer structure is introduced and all the basic building blocks are analyzed; for each of them it has been implemented a model: the realization methodology is presented and discussed in detail. The focus is put on the analysis of the Transmitter, the PCB interconnection, the Receiver, the Phased Locked Loops (PLLs) and the Clock and Data Recovery (CDR). Chapter 3 analyzes the fundamental parameters that determine the performances of a Physical Layer; the construction and the use of the Eye diagram are presented together with the actions to extract timing information and, then, to perform a budget. The various types of jitter and the corresponding causes are discussed. A statistical abstraction is introduced toward the computation of the Bit Error Rate (BER). In Chapter 4, it is illustrated the theory behind a MATLAB script that analyzes the channel pulse response to extract worst-case scenarios and to study the impact of a simple equalizer stage on the overall PHY’s performances; the design key-parameters of this block are then extracted and used in a VHDL-AMS implementation

Modeling and Simulation for Signal and Power Integrity in Mobile Platforms

This tutorial will cover technological, architectural, modeling and simulation challenges for the Signal and Power Integrity of high-end mobile platforms. On one hand, the latest packaging technologies for mobile applications will be discussed, emphasizing their pros and cons in view of current and expected future system requirements. On the other hand, the architectural challenges will be translated into modeling and simulation challenges, that engineers have to face in their daily work for ensuring system-level signal and power quality. Fast simulation approaches based on reduced-order behavioral models for both interconnects and devices will be discussed in detail. Finally, case studies from real mobile applications will be illustrated

Behavioral macromodeling of high-speed drivers via compressed tensor representations

This paper addresses the behavioral modeling of digital drivers for Signal and Power Integrity co-simulations. State-of-the-art two-piece model representations are combined with a compact description of the device static characteristics. The latter are considered as multivariate mappings that are functions of the device electrical variables, and of additional parameters defining process corners and device settings. Overall model complexity is reduced through a compressed tensor representation obtained via a high-order singular value decomposition. Several application examples demonstrate the feasibility and the advantages of the proposed approac

Detection and isolation of circulating tumor cells with single-cell resolution: A successful lab-on-a-chip device

This paper was presented at the 3rd Micro and Nano Flows Conference (MNF2011), which was held at the Makedonia Palace Hotel, Thessaloniki in Greece. The conference was organised by Brunel University and supported by the Italian Union of Thermofluiddynamics, Aristotle University of Thessaloniki, University of Thessaly, IPEM, the Process Intensification Network, the Institution of Mechanical Engineers, the Heat Transfer Society, HEXAG - the Heat Exchange Action Group, and the Energy Institute.This paper presents the unique features of DEPArray™ an automated system enabling image-based cell sorting with single-cell resolution and describes its potential application in the field of oncology

Molecular profiling of single circulating tumor cells with diagnostic intention

Several hundred clinical trials currently explore the role of circulating tumor cell (CTC) analysis for therapy decisions, but assays are lacking for comprehensive molecular characterization of CTCs with diagnostic precision. We therefore combined a workflow for enrichment and isolation of pure CTCs with a non-random whole genome amplification method for single cells and applied it to 510 single CTCs and 189 leukocytes of 66 CTC-positive breast cancer patients. We defined a genome integrity index (GII) to identify single cells suited for molecular characterization by different molecular assays, such as diagnostic profiling of point mutations, gene amplifications and whole genomes of single cells. The reliability of >90% for successful molecular analysis of high-quality clinical samples selected by the GII enabled assessing the molecular heterogeneity of single CTCs of metastatic breast cancer patients. We readily identified genomic disparity of potentially high relevance between primary tumors and CTCs. Microheterogeneity analysis among individual CTCs uncovered pre-existing cells resistant to ERBB2-targeted therapies suggesting ongoing microevolution at late-stage disease whose exploration may provide essential information for personalized treatment decisions and shed light into mechanisms of acquired drug resistance

Molecular profiling of single circulating tumor cells with diagnostic intention

Several hundred clinical trials currently explore the role of circulating tumor cell (CTC) analysis for therapy decisions, but assays are lacking for comprehensive molecular characterization of CTCs with diagnostic precision. We therefore combined a workflow for enrichment and isolation of pure CTCs with a non-random whole genome amplification method for single cells and applied it to 510 single CTCs and 189 leukocytes of 66 CTC-positive breast cancer patients. We defined a genome integrity index (GII) to identify single cells suited for molecular characterization by different molecular assays, such as diagnostic profiling of point mutations, gene amplifications and whole genomes of single cells. The reliability of >90% for successful molecular analysis of high-quality clinical samples selected by the GII enabled assessing the molecular heterogeneity of single CTCs of metastatic breast cancer patients. We readily identified genomic disparity of potentially high relevance between primary tumors and CTCs. Microheterogeneity analysis among individual CTCs uncovered pre-existing cells resistant to ERBB2-targeted therapies suggesting ongoing microevolution at late-stage disease whose exploration may provide essential information for personalized treatment decisions and shed light into mechanisms of acquired drug resistance

Modeling and Simulation for Signal and Power Integrity of Next-Generation High-Speed Physical Layers

The amount of data being transferred across different components of the most modern computing platforms is continuously growing. High-speed wired communication interfaces have been constantly improved over the last years, increasing transmission data-rate, minimizing pin-count and reducing power consumption; this is particularly true in mobile platforms (cellular phones, smart-phones, tablets, etc.), where specialized communication protocols and processing units are specifically designed for a maximum optimization of power efficiency and prevention of electromagnetic interference (EMI). Communication interfaces can support different speeds and voltage levels, adjusted according to the target application (communication to other chips, cameras, displays, batteries, RF transceivers, etc.). The high-level of integration in state-of-the-art Printed Circuit Boards (PCB), Packages, Systems-in-a-Package (SiP) and Systems-on-Chip (SoC), combined with the inevitable presence of resistive, inductive and capacitive parasitic components of the interconnection structures, often leads to severe system performance degradation. Signal and Power Integrity simulations are required to study the impact of interconnection non-idealities on communication reliability and quality (electrical levels, signal distortions, power-supply fluctuations, Bit-Error-Rate (BER), etc.). Macromodel-based simulations appear to be the only viable approach to deal with the complexity of such analyses: transmitter and receiver circuits (I/Os), usually described by detailed transistor-level netlists, are substituted with accurate and efficient equivalent representations; simulations run much faster, accuracy is guaranteed and system-level verification coverage can be extended. However, I/O macromodeling has become a more and more challenging task: the increasing communication speed (up to 10Gbps) and the reduction of signal amplitudes require outstanding model accuracy; furthermore, several detrimental effects can be induced by supply-voltage fluctuations, originated by the combination of power distribution network (PDN) non-idealities and I/O dynamic current consumption. Nowadays, the standard approach for I/O buffer modeling is offered by the Input/Output Buffer Information Specification (IBIS) [5]. IBIS suggests simplified circuit equivalents of typical buffer structures and provides detailed guidelines for the collection of relevant device features via a ready-to-use extraction procedure (e.g., the static characteristics of the output port current, the equivalent capacitance of the silicon die, ...). This specification has been massively used for generating buffer models and it has been continuously updated with additional features and enhancements, becoming a de-facto standard. In spite of the widely recognized importance and diffusion of IBIS, some specific features of modern I/O devices cannot be accurately reproduced; mostly, the inaccuracies appear to be related with the power supply currents and the dynamic dependence of I/O and supply voltages on circuit’s behavior. In literature, other approaches are available [7, 17, 18, 19, 20, 21, 22]: they complement IBIS and provide improved model accuracy and reasonable efficiency. However, all these approaches do not offer a conclusive reliable tool that accommodates for both single ended and differential devices, with a robust modeling procedure and a satisfying accuracy for high-performance I/O-buffers in complex simulation scenarios. This research work suggests general and modular modeling solutions, derived from the simple observation of only device external port responses and able to meet all the behavioral requirements. Starting from state-of-the-art macromodeling techniques described in [4, 5, 6] and [7], this research work proposes enhanced Mpilog macromodels [24, 31, 32]. Results presented in [24] have been acknowledged with the IEEE Best Student Paper Award at 2015 IEEE Signal and Power Integrity, Berlin, Germany, in May 2015. The model structure is defined by two-piece representations that combine multivariate static surfaces and linear dynamical state-space relations. The static parts are conveniently modeled with compressed tensor approximations [28, 24], thus facilitating their SPICE equivalent synthesis and able to run in any commercial SPICE tool. The dynamical parts are identified using robust time-domain vector fitting algorithms [2, 30]. Overclocking operation is supported and handled by imitating the behavior of the real switching mechanism of output buffers via a simple and reliable solution. Once implemented, the models offer remarkable accuracy and good efficiency figures. Furthermore, this research has carried out a thorough critical analysis of all the stateof-the-art I/O-buffer macromodeling methodologies, with special focus on the investigation of performance and limitations of IBIS models. Results have been presented in [33], and findings have been acknowledged by the IBIS standardization committee [34]. This research work proposes also e-IBIS, a set of enhancements to the current IBIS specification that have been proven to significantly extend model accuracy in signal and power integrity co-simulation scenarios (see Chapter. 5). Chapter 1 illustrates state-of-the-art physical implementation techniques of most modern package, PCB and platforms for mobile consumer electronics; characteristics and performances of high-speed physical layers (PHY) for wired communication interfaces are also briefly discussed. Afterwords, signal and power integrity simulation methodologies and challenges are presented, with focus on the requirements for model-based analyses. Chapter 2 presents the results of a thorough review of state-of-the-art macromodeling techniques for I/O-buffers; model performances and limitations are demonstrated using real system and devices implementations. Chapter 3 introduces enhanced Mpilog macromodels, discussing and justifying the improvements applied to each model sub-component. Chapter 4 presented the set of enhancements that this research work has identified and suggested to improve IBIS standard models. Chapter 5 provides extensive demonstrations of the resulting accuracy of enhanced models; simulations are based on real complex simulation scenarios for single-ended and differential communication interfaces. Appendix A provides a detailed description of the iterative SVD approximation used to map multi-variate model sub-components; Appendix B, referring to [2], gives an overview on Frequency-Domain and Time-Domain Vector-Fitting algorithms, used for identification and representation of multi-input multi-output dynamic model sub-components. This thesis eventually ends drawing conclusions on the research findings and outlining open challenges and trends in I/O-buffer macromodeling and model-based signal and power integrity simulations