Conceptualization of Spiritual Education in Seyyed Hosein Nasr`s Thoughts and Comparing It with the Current Definitions

The aim of this article is to probe the concept of spiritual education in Seyyed Hosein Nasr`s thoughts and to compare it with the current definitions of the concept. This study has been done through the qualitative method called transcendental analysis. Therefore, that concept was conceptualized through investigating and eliciting the requisite assumptions from Nasr`s philosophical approach. Findings showed that in Nasr`s thoughts, spiritual education is the process of actualizing all the innate potentialities of human as a whole towards his or her monotheistic nature through developing knowledge, love, righteous actions and acquiring virtues to transcend his or her existential layers to train his or her spirit, to know the Ultimate Reality and to return to his or her prototype in God. It is acquirable by taking action based on a heavenly religion. The aim of spiritual education is to know the Ultimate Reality intuitively. Compared to the current definitions, the concluded concept is more similar to that of Carr’s and Tabatabaie’s ideas while it is different from Miller, Duff and Bigger’s perspectives. Keywords: spirituality; spiritual education; conceptual comparison; Seyyed Hosein Nasr

Yield, Cost, Reliability, and Availability of Multi-Core System-on-Chips

Aggressive technology scaling has magnified the reliability challenges as it increases the number of permanent and transient faults due to the accelerated aging, increased device variations, and significant noise margin reduction. In this thesis, we address the key challenges of the yield and reliability of NoC-based SoCs which include cores, on-chip communications, and on-chip memories. Our yield and cost analysis shows that by adding a limited number of spare cores and wires to replace defective cores and wires either before shipment or in the field, the effective yield, in-field availability, and overall cost of the system can be significantly improved and the burn-in process can be eliminated. We also propose a quality metric for on-chip communication which can be used along with the frequency binning to price the chip in the market. We demonstrate that the overall quality of a mesh-based NoC depends more on the reliability of the inner links, and hence, non-uniform spare wire distribution is more effective than a uniform approach. For the reliability of the on-chip memories, we propose error-locality-aware codes to correct single-bit or multi-bit upsets as well as physical defects in SRAM cells. With the same cost as Golay and BCH codes, our proposed codes provide better reliability against multi-bit upsets. We propose an interleaved error-locality-aware code to be used for end-to-end error correction in on-chip communications. In order to maintain the error correction capability of the code for transient and intermittent errors, we further propose an end-to-end data gathering and online diagnosis approach that locates the defective wires and replaces them with the spare wires embedded in the network

End-to-end error correction and online diagnosis for on-chip networks

Abstract In an on-chip network, roughly 80 % of the communication faults are transient [9]. Different fault tolerance approaches such as Forward Error Control (FEC), Automatic Repeat Query (ARQ), and multi-path routing have been used and compared in literature for reliable on-chip transmission [15-17]. These approaches tolerate transient faults, but they become ineffective in the presence of permanent faults. Permanent faults on wires occur both during manufacturing and in the field, causing yield degradation and service costs respectively. The overall system cost can be reduced by adding some spare wires per each link of the network to replace the defective wires [15,18]. Nevertheless, an in-field diagnosis mechanism is required to locate the defective wire and initiates the wire replacement. We propose a comprehensive solution for end-to-end (e2e) error correction and online defect diagnosis for on-chip networks. For e2e error correction, we propose an interleaved error-locality-aware code that efficiently corrects both random and burst errors. We demonstrate that for 64-bit wide network links, interleaving four of the proposed code, 2G4L(26,16), each of which supports 16-bit data, can correct as many as two random errors or 16 adjacent errors. In order to maintain the error correction capability of the Error Correcting Code (ECC) for transient and intermittent errors, we further propose an e2e data gathering and online diagnosis approach that locates the defective wires and replaces them with the spare wires embedded in the network. Our analytical and experimental studies show that under heavy noise, high escape rate, uncertainty about routing, and many other harmful effects, the diagnostic data collected by the proposed approach are accurate enough for the purpose of passive diagnosis. 1

A Genetic-Algorithm Solution for Designing Optimal Forwarding Tables

Abstract. A high speed IP address lookup engine with a reasonable memory cost is a key factor for designing a router at wire speed. This paper proposes a hardware solution that performs each IP address lookup in a few number of memory accesses with minimum amount of memory requirement. Our solution is based on dividing destination IP address into several segments. For finding the optimum address segmentation that minimizes the memory consumption, a genetic-algorithm solution is employed. The genetic program uses benchmark forwarding tables for finding the optimum points of address segmentation. The final result is a small forwarding table for the local traffic of the router. This table can be reconfigured along the time when the local traffic gradually changes. The proposed method can fit a forwarding table of size 130000 routing prefixes in about 1.5 MB of memory with only four memory accesses for each lookup search.

Measuring the Reliability of Sagittal Facial Anthropometric Measurements under Soft Tissue Displacement Using a Modified Ruler

Objective: Despite the current use of radiography for quantifying sagittal skeletal measurements, it is an unsuitable way for screening or epidemiologic purposes. Although not fully approved, anthropometric measurements have been suggested as a substitute, and considering displacement of soft tissues, could possibly lead to more consistent results. The purpose of this study was to evaluate the reliability of anthropometric anteroposterior facial measurements under soft tissue compression using a special ruler.Material and Methods: Anthropometric measurements were done with a specifically designed sliding ruler twice on 36 adult patients with a 14 day lag between two measurements. The ruler measured the distance between the external acoustic meatus and the nasion (Na), subnasal (Sn) point and the soft tissue pogonion (Pog). The soft tissue was displaced during measurements only to the extent that the underlying hard tissue resistance was felt subjectively by each assessor. The intraclass correlation coefficient (ICC) was calculated for both inter- and intra- rater measurements using SPSS software.Results: All measurements had inter- and intrarater agreements above 0.9, with only a few parameters having lower bound confidence intervals below 0.9, but more than 0.8.Conclusion: Sagittal facial anthropometric measurements under soft tissue displacement using the specific ruler are valid and reliable and could possibly aid orthodontists in chairside craniofacial assessments

A Cost Analysis Framework for Multi-core Systems with Spares

It becomes increasingly difficult to achieve a high manufacturing yield for multi-core chips due to larger chip sizes, higher device densities, and greater failure rates. By adding a limited number of spare cores to replace defective cores either before shipment or in the field, the effective yield of the chip and its overall cost can be significantly improved. In this paper, we propose a yield and cost analysis framework to better understand the dependency of a multi-core chip’s cost on key parameters such as the number of cores and spares, core yield, and defect coverage of manufacturing and in-field testing. Our analysis shows that we can eliminate the burn-in process when we have some spare cores for in-field recovery. We demonstrate that a high defect coverage for in-field testing, a necessity for supporting in-field recovery, is essential for overall cost reduction. We also illustrate that, with in-field recovery capability, the reliance on high quality manufacturing testing is significantly reduced. 1