Evolving Linear Discriminant in a Continuously Growing Dimensional Space for Incremental Attribute Learning

Part 12: DATICSInternational audienceFeature Ordering is a unique preprocessing step in Incremental Attribute Learning (IAL), where features are gradually trained one after another. In previous studies, feature ordering derived based upon each individual feature’s contribution is time-consuming. This study attempts to develop an efficient feature ordering algorithm by some evolutionary approaches. The feature ordering algorithm presented in this paper is based on a criterion of maximum mean of feature discriminability. Experimental results derived by ITID, a neural IAL algorithm, show that such a feature ordering algorithm has a higher probability to obtain the lowest classification error rate with datasets from UCI Machine Learning Repository

Recursive self organizing maps with hybrid clustering

10.1109/ICCIS.2006.2522682006 IEEE Conference on Cybernetics and Intelligent Systems

Cryptanalysis of an Image Encryption Scheme Using Cellular Automata Substitution and SCAN

Department of Electronic and Information EngineeringRefereed conference pape

The New Small Wheel electronics

The increase in luminosity, and consequent higher backgrounds, of the LHC upgrades require improved rejection of fake tracks in the forward region of the ATLAS Muon Spectrometer. The New Small Wheel upgrade of the Muon Spectrometer aims to reduce the large background of fake triggers from track segments that are not originated from the interaction point. The New Small Wheel employs two detector technologies, the resistive strip Micromegas detectors and the "small" Thin Gap Chambers, with a total of 2.45 Million electrodes to be sensed. The two technologies require the design of a complex electronics system given that it consists of two different detector technologies and is required to provide both precision readout and a fast trigger. It will operate in a high background radiation region up to about 20 kHz/cm$^{2}$ at the expected HL-LHC luminosity of $\mathcal{L}$=7.5$\times10^{34}$cm$^{-2}$s$^{-1}$. The architecture of the system is strongly defined by the GBTx data aggregation ASIC, the newly-introduced FELIX data router and the software based data handler of the ATLAS detector. The electronics complex of this new detector was designed and developed in the last ten years and consists of multiple radiation tolerant Application Specific Integrated Circuits, multiple front-end boards, dense boards with FPGA's and purpose-built Trigger Processor boards within the ATCA standard. The New Small Wheel has been installed in 2021 and is undergoing integration within ATLAS for LHC Run 3. It should operate through the end of Run 4 (December 2032). In this manuscript, the overall design of the New Small Wheel electronics is presented.Comment: 61 page