A 1 Volt Switched Transconductor Mixer in 0.18μm CMOS

A new CMOS mixer topology can operate at low supply voltages by using switches connected only to the supplies. Mixing is achieved exploiting two cross-coupled transconductors, which are alternatingly activated by the switches. A down conversion mixer prototype with 12 dB conversion gain was designed and realized in standard 0.18 μm CMOS. It achieves satisfactory mixer performance up to 4 GHz, at a supply voltage of 1 Volt. Moreover, the mixer topology features a fundamental high frequency noise figure benefit

Time-interleaved track and hold

The present application relates to an apparatus comprising a first transistor element, with at least three terminals, and at least one switching unit. The present application relates also to a method, computer readable medium having a computer program stored thereon and a track and hold circuit comprising the apparatus. The apparatus comprises a first transistor element with at least three terminals, wherein a first terminal is supplied with a first voltage, and wherein a second terminal is supplied with a second voltage. The apparatus comprises a first switching unit, wherein a third terminal is connected to ground potential via the first switching unit. The transistor element comprises a predefined threshold voltage. The first voltage and the second voltage are predefined alternating voltages.; The transistor element is configured such that in case a differential voltage between the first predefined alternating voltage and the second predefined alternating voltage is higher than the predefined threshold voltage and the first switching unit is not conductive the third terminal is charged with the first predefined alternating voltage

Circuit with a successive approximation analog to digital converter

During successive approximation analog to digital conversion a series of successive digital reference values is selected that converges towards a digital representation of an analog input signal. An analog reference signal is generated dependent on the successive digital reference values and compared to the analog input signal. The digital reference values are selected dependent on comparison results. In the selection of the digital reference values successive steps between digital reference values are each selected dependent on values of the comparator result from a plurality of preceding recursion cycles. The comparison results define a series of successively narrower ranges of digital values that contain a digital representation of the analog input signal. Use of a plurality of comparator results for selecting the steps in the digital reference values makes it possible to reduce uncertainty about whether the comparison result has settled. This in turn makes it possible to reduce the sizes of the successive ranges, which speeds up convergence

Mixer circuit, receiver comprising a mixer circuit, wireless communication comprising a receiver, method for generating an output signal by mixing an input signal with an oscillator signal

The invention relates to a mixer circuit comprising an input node for receiving an input signal, a first output node 202, and a second output node 203, voltage to current conversion means and switching means operatively coupled to each other and to the input node, the first output node and the second output node to generate a mixed input signal at the first output node and the second output node in response to an oscillator signal. In an embodiment the voltage to current conversion means comprises a first and a second voltage to current converter, implemented as N-MOSFETs M2 and M3, with their gates connected to the input node. The drain of M2 is connected to the first output node 202, while the drain of the M3 is connected to the second output node M3. The source of M2 is connected to the switching node 221, while the source of M3 is connected to the second switching node 222. The switches SW are arranged to couple the first switching node 221 to a first supply voltage VDD and the second switching node 222 to a second supply voltage VSS during a first phase of the oscillator signal, and the first switching node 221 to VDD and the second switching node 222 to VSS during a second phase of the oscillator signal. The mixer circuit according to the invention may operate at low supply voltages by using switches connected only to the supply voltages VSS and VDD. Mixing is achieved by voltage to current converters GM1 and GM2, which are alternatingly activated by the switches SW

A 1.35 GS/s, 10b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS

A time-interleaved ADC is presented with 16 channels, each consisting of a track-and-hold (T&H) and two successive approximation (SA) ADCs in a pipeline configuration to combine a high sample rate with good power efficiency. The single-sided overrange architecture achieves a 25% higher power efficiency of the SA-ADC compared with the conventional overrange architecture, and look-ahead logic is used to minimize logic delay in the SA-ADC. For the T&H, three techniques are presented enabling a high bandwidth and linearity and good timing alignment. Single channel performance of the ADC is 6.9 ENOB at an input frequency of 4 GHz. Multichannel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz. The FoM of the complete ADC including T&H is 0.6 pJ per conversion step. An improved version is presented as well and achieves an SNDR of 8.6 ENOB for low sample rates, and, with increased supply voltage, it reaches a sample rate of 1.8 GS/s with 7.9 ENOB at low input frequencies and an ERBW of 1 GHz. At fin = 3.6 GHz, the SNDR is still 6.5 ENOB, and total timing error including jitter is 0.4 ps rms

Time-Interleaved Analog to Digital Converters

This book describes the research carried out by our PhD student Simon Louwsma at the University of Twente, The Netherlands in the field of high-speed Analogto- Digital (AD) converters. AD converters are crucial circuits for modern systems where information is stored or processed in digital form. Due to increasing data rates and further digitization of systems, the demands on the AD converters are increasing in both sample-rate and number of bits. A fast and accurate AD converter combined with digital signal processing offers an attractive alternative for the analog signal chain still present in many actual receivers. This book offers an exploration of fundamental and practical limits of high speed AD conversion, aiming at a step forward in number of bits and sample-rate, while keeping the power consumption low. To achieve high performance, a technique called time interleaving is used. Time interleaving is the analog equivalent of parallel processing in the digital domain. To implement this, instead of a single Track-and- Hold (T&H), we use a whole series of them, each sampling a bit later than the previous one. In the design example in this book we use 16 T&H circuits, followed by 16 sub-AD converters. The timing alignment of these T&H circuits needs to be extremely accurate, and conventionally, complex timing calibration is used to achieve this. Here however, it is shown that even better performance can be achieved by a compact and good design of the timing circuit without requiring any timing calibration. The circuits use a minimum of transistors that cause timing inaccuracies and special layout techniques are the finishing touch. Thanks to the absence of a control range for the timing, the amount of jitter is also reduced. To save power and to keep the input capacitance low, small sized transistors are used in the time-interleaving T&H circuitry. Only simple DC calibrations are needed to make the 16 paths behave equally over the whole input frequency range. An extensive analysis of accuracy and timing requirements is given and circuit solutions are described in detail. After the input signal is sampled by a T&H section, a sub-ADC finalizes the conversion. Pipeline AD converters are popular for conversion rates around 100 MS/s, but they suffer from the fact that even in the first stage of the pipeline the full accuracy for settling is required. This makes the design of high speed in combination with a high accuracy quite a challenge. Instead of that, we use sub-ADCs based on Successive Approximation (SA). As explained in this book, this has quite some advantages: A SAR ADC contains less critical analog blocks, and its power consumption can be ten times less than a comparable pipeline ADC. A potential disadvantage of Successive Approximation converters is the relatively low maximum sample-rate. This problem is tackled with a new overrange technique that greatly reduces the demands on settling time per conversion step and that postpones the critical decision to the last conversion step. This offers great advantage over a Pipeline ADC, where the first residue amplifier must settle to full accuracy to avoid unrecoverable analog errors in the conversion process. The work described in this book shows state-of-the art performance and describes techniques, which gain popularity among today’s AD converter designers. We enjoyed carrying out the research with Simon and we hope you will enjoy reading the results