Parametrizable Architecture for the Motion Estimator Chip

this paper a parametrizable architecture of a motion estimator is presented. The architecture supports the H.263 standard but can be adopted for other video standards as well. The parameters by which the motion estimator is described allow for a variety of architecture configurations. The parameters specify the level of parallelism, the algorithmic pipelining, and the use of configurable cache memories. VLSI implementation is performed by Cathedral-2/3, a high-level synthesis environment for high-speed applications. 1. INTRODUCTIO

Hardware/software partitioning of embedded system in ocapi-xl

The implementation of embedded networked appliances requires a mix of processor cores and HW accelerators on a single chip. When designing such complex and heterogeneous SoCs, the HW / SW partitioning decision needs to be made prior to refining the system description. With OCAPI-xl, we developed a methodology in which the partitioning decision can be made anywhere in the design flow, even just prior to doing code-generation for both HW and SW. This is made possible thanks to a refinable, implementable, architecture independent system description. The OCAPI-xl model was used to develop a stand alone, networked camera, with onboard GIF engine and network layer. 1

Hierarchical Run-Time Reconfiguration Managed by an Operating System for Reconfigurable Systems

The need for flexible computational power has motivated many researchers to incorporate run-time reconfigurable logic into their architectures. Most contemporary experiments include commercial FPGA's serving as reconfigurable hardware. Unfortunately, the FPGA does not exhibit the same run-time flexibility as the Instruction Set Processor (ISP) e.g. when it comes to ease and speed of setting up a task. In addition, FPGA's tend to be less suited than traditional ISP's to accommodate control-flow dominated tasks. Obviously, it is possible to alleviate some of these issues by using a reconfiguration hierarchy (e.g. placing and configuring an ASIP or coarse grain reconfigurable block into the FPGA). This paper illustrates how our operating system transparently manages the complexity of hierarchical reconfiguration. In addition, this paper highlights the benefits and drawbacks of employing multiple hierarchical levels of configuration. As a proof of concept, we developed a filtering application on top of an in-house 16 bit microcontroller and a parameterizable filter block, both instantiated inside an FPGA

Networks on Chip as Hardware Components of an OS for Reconfigurable Systems

Abstract. In complex reconfigurable SoCs, the dynamism of applications requires an efficient management of the platform. To allow run-time allocation of resources, operating systems and reconfigurable SoC platforms should be developed together. The operating system requires hardware support from the platform to abstract the reconfigurable resources and to provide an efficient communication layer. This paper presents our work on interconnection networks which are used as hardware support for the operating system. We show how multiple networks interface to the reconfigurable resources, allow dynamic task relocation and extend OS-control to the platform. An FPGA implementation of these networks supports the concepts we describe.

Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis

This paper presents the design of a Videophone CoderDecoder Motion Estimator using two High-Level Synthesis tools. Indeed, the combination of a Control Flow Dominated part (complex communication protocol) with a Data Flow Dominated part (high throughput computations) makes this circuit difficult to be synthesized by a single HLS tool. The combination of two HLS tools for the high-level design of this operator required the definition of a sophisticated design flow allowing mixed-level and multi-language simulations. When compared to design starting from RTL specifications, HLS induces only a negligible area overhead of 5%, and provides gain in description length (divided by 5), design time and flexibility

Interconnect-aware mapping of applications to coarse-grain reconfigurable architectures

Coarse-grain reconfigurable architectures consist of a large number of processing elements (PEs) connected together in a network. For mapping applications to such coarse-grain architectures, we present an algorithm that takes into account the number and delay of interconnects. This algorithm maps operations to PEs and data transfers to interconnects in the fabric. We explore three different cost functions that largely affect the performance of the scheduler: (a) priority of the operations, (b) affinity of operations to PEs based on past mapping decisions, and (c) connectivity between the PEs. Our results show that a priority-based operation cost function coupled with a connectivity-based PE cost function gives results that are close to the lower bounds for a range of designs

Highly Scalable Network on Chip for Reconfigurable Systems

An efficient methodology for building the billiontransistors systems on chip of tomorrow is a necessity. Networks on chip promise to be the solution for the numerous technological, economical and productivity problems. We believe that different types of networks will be required for each application domains. Our approach therefore is to have a very flexible network design, highly scalable, that allows to easily accommodate the various needs. This paper presents the design of our network on chip, which is part of the platform we are developing for reconfigurable systems. The present design allows us to instantiate arbitrary network topologies, has a low latency and a high throughput.