Noise immunity of digital circuits in mixed-signal smart power systems

Abstract | Experimental data describing circuit and physical design issues that in uence the noise immunity of digital latches in mixed-signal smart power circuits are described and discussed. The principal result of this paper is the characterization of the conditions under which substrate noise generated by high power analog circuitry a ects digital latches. The experimental data characterize a variety of di erent noise mitigation techniques for the particular process technology, circuit structures, signal/clocking interdependencies, and related conditions. I

Substrate Coupling in Digital Circuits in Mixed-Signal Smart-Power Systems

Abstract—This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such digital circuits are identified and analyzed. The results are obtained primarily from a set of dedicated test circuits specifically designed, fabricated, and evaluated for this work. The conclusions drawn from the theoretical and experimental analyses are used to develop physical and circuit design techniques to mitigate the substrate noise problems. These results provide insight into the noise immunity of digital circuits with respect to substrate coupling. Index Terms—Noise, smart-power, substrate coupling. I