Addressing quality and usability of surface water bodies in semi-arid regions with mining influences

Water resources management has considerable importance, specifically in the context of climate change. This subject has introduced new challenges in semi-arid regions with water quality problems, such as the Iberian Pyrite Belt, which is one of the largest metallogenetic provinces in the world and one of the driest regions in Europe. Positioned in the Mediterranean context, the region has a high density of polymetallic sulphide mines that promote the degradation of water systems. The present study aims to assess the water quality in the Pyrite Belt, considering a total of 34 surface water bodies, including constructed reservoirs, permanent and ephemeral streams, and mining facilities with accumulated water (e.g., pit lakes and mining dams). The water samples were analysed for physico-chemical properties, including field parameters (pH, electrical conductivity), alkalinity/acidity, hardness, anions, and potential toxic elements. The results were used for hydrochemical classifications and the assessment of suitability for public uses. Statistical methods, such as hierarchical cluster analysis and nearest centroid classifier, were used for grouping and evaluating the similarity between water bodies. Two groups were generated from the analysis: i) constructed lakes with alkaline and sodium signatures; and ii) waters suffering from the influence of mining wastes, e.g., showing high acidity, sulphate and metal contents. Therefore, the loss of water quality in the vicinity of mines reflects the impact of acid mine drainage. The methodological approach used may be applied to the integrated management of water resources in regions with mining influences and where it is necessary to combat drought and water scarcity scenarios.Patricia Gomes acknowledge FCT (Science and Technology Foundation, Portugal) by the research fellowship under the POCH (Programa Operacional Capital Humano) supported by the European Social Fund and National Funds of MCTES (Ministerio da Ciencia, Tecnologia e Ensino Superior) with reference SFRH/BD/108887/2015. This work was co-funded by the European Union through the European Regional Development Fund, based on COMPETE 2020 (Programa Operacional da Competitividade e Internacionalizacao) - project ICT (UID/GEO/04683/2013) with reference POCI-01-0145-FEDER-007690 and project Nano-MINENV number 029259

SoC energy savings = reduce+reuse+recycle: A case study using a 660MHz DC-DC converter with integrated output filter

This paper advocates 'reduce, reuse, recycle' as a complete energy savings strategy. While reduction has been common to date, there is growing need to emphasize reuse and recycling as well. We design a DC-DC buck converter to demonstrate the 3 techniques: reduce with low-swing and zero voltage switching (ZVS), reuse with supply stacking, and recycle with regulated delivery of excess energy to the output load. The efficiency gained from these 3 techniques helps offset the loss of operating drivers at very high switching frequencies which are needed to move the output filter completely on-chip. A prototype was fabricated in 0.18μm CMOS, operates at 660MHz, and converts 2.2V to 0.75-1.0V at ∼50mA.1 © 2008 IEEE

A 660MHz ZVS DC-DC converter using gate-driver charge-recycling in 0.18μm CMOS with an integrated output filter

The design and manufacture of a prototype chip level power supply is described, with both simulated and experimental results. Of particular interest is the inclusion of a fully integrated on-chip LC filter. A high switching frequency of 660MHz and the design of a device drive circuit reduce losses by supply stacking, low-swing signaling and charge recycling. The paper demonstrates that a chip level converter operating at high frequency can be built and shows how this can be achieved, using zero voltage switching techniques similar to those commonly used in larger converters. Both simulations and experimental data from a fabricated circuit in 0.18μm CMOS are included. The circuit converts 2.2V to 0.75∼1.0V at ∼55mA. ©2008 IEEE