Impact of Computing-in-Memory on the Performance of Processor-and-Memory Hierarchies

A Hierarchy of Processor-And-Memory (HPAM) can be viewed as an extension of the notion of a memory hierarchy. The extension entails the inclusion of processors with di erent performance in di erent levels of the memory hierarchy. Technology trends, applications behavior and previous research suggest that a multiprocessor system organized as a Hierarchy of Processor-And-Memory may o er considerable advantages over conventional multiprocessor organizations. This paper quanti es and analyzes the advantages of computing-in-memory, for a multi-level HPAM system, as compared toaconventional multiprocessor system with the same cost. The analysis entails using performance models and simulation data. Underlying the comparative study is the assumption that the cost of a processor is in proportion to the square of its performance. The 9 benchmarks used in the evaluations belong to the CMU, Perfect Benchmarks and SPEC95 suites. While the evaluation methodology takes into account the heterogeneity of HPAM, the emphasis is placed onmodeling the impact of computingin-memory on the relative performance of the multiprocessors under study. The results indicate that, with rare exceptions, HPAM outperforms conventional multiprocessor designs of identical cost by as much a 80% in the benchmarks and the ranges of model parameters considered in the study. In the very few exceptions to this conclusion HPAM is never outperformed by more than 20%

On the Integration of Computer Architecture and Parallel Programming Tools into Computer Curricula Abstract

Tools for computer architecture design and parallel programming have become essential to practicing computer architects and software developers in industry. There is signi cant demand for designers who can develop, use and modify them. More importantly, design and simulation tools capture fundamental engineering concepts that should be mastered by computer professionals. This paper describes an approach to the integration of tools for computer architecture simulation, performance prediction, program optimization and application characterization into computer science and engineering curricula. The approach is based on a unique, operational distributed infrastructure- the Purdue University Network Computing Hubs (PUNCH). The PUNCH infrastructure lets users with di erent computing platforms run a broad range of tools via standard WWW browsers. PUNCH also allows universities to share course-development e orts, tool expertise and resources while preserving the appearance of a centralized point of access to all tools installed in PUNCH. The expected outcomes of this project are: (1) generations of computer architecture and software designers who are capable of understanding and using state-of-the-art, industrially-relevant tools and (2) an infrastructure model for inter-university cooperation in curriculum improvement and resource sharing that can be extended/replicated across other institutions interested in incorporating computer design tools in their curricula. I

A Network-Computing Infrastructure for Tool Experimentation Applied to Computer Architecture Education

Computer architects increasingly depend on the use of software tools to evaluate and investigate the design of computer systems. It is therefore very important that educators in this eld promote extensive tool-based student experimentation in architecture classes. However, the integration of today's complex architecture tools into curricula poses several challenges to an instructor, including managementofpowerful computing resources, software installation and maintenance, and development of tool-speci c educational material. This paper describes how these challenges are addressed by a universally accessible network-computing infrastructure- NETCARE- that provides educators with a Web portal to access computing resources, executable tools and educational material.