Platform-Based Design for Space Applications

This paper presents a platform-based approach adopted to develop a sensor interface for a generic spacequalified sensor. The design environment is composed by hardware blocks and software tools suitable for the design space exploration, while a proper verification methodology intents to guarantee the correct system behavior and to increase its reliability. An application case with a rate gyro sensor is being considered in order to tune the design flow. The approach aims to reduce the costs of the final chip in terms of either the development time, by exploiting the platform concept, or the involved circuitry, for the massive usage of the digital electronic in spite of the analog one

Generic Sensor Interface for on-Board Satellite Applications

Satellite demands in terms of computational power, dimensions, mass, reliability and power consumption related to the electronic circuitry for on-board-processing (both payload and house keeping operations) are typically addressed with integrated solutions: System-on-Chip (SoC) has become a familiar term which identifies a complex heterogeneous system composed by one or more processing units, an application specific block-set and a variable number of general purpose [programmable] peripherals (communication, networking, memories). New design methodologies are required for the design and verification of such a complex SoC in a reasonable time. In this paper we applied the so called platform based approach for the development of a generic digital sensor interface: the interface gathers the data coming from a space qualified sensor and after a proper signal conditioning (offset calibration, linearization, thermal compensation) provides the processed information through a SpaceWire link

Highly Efficient Wideband Digital Frequency Demultiplexer

This paper presents an advanced ASIC architecture for a wideband digital frequency demultiplexer designed for on board satellite communication systems. The structure is able to handle up to 32 uniformly spaced channels extracted from a digital, real frequency division multiplexed signal sampled at 672 MHz; contiguous demultiplexing and remultiplexing is supported. An efficient demux two-stage parallel architecture was developed where all internal coefficients (including the FFT ones) are coded with canonic signed digit technique allowing area saving with respect to 2's complement code. Performance evaluations, in terms of bit error rate, noise to power ratio and gate complexity, were carried out for the architecture definition. Subsequently the design was coded in VHDL and synthesised on a 0.18 μm CMOS technology by means of Synopsys™ tools

Sensor Platform Design for Automotive Applications

This paper presents a prototyping environment suited to fast identify, trim and verify a digital sensor interface in the automotive field, and to make early performance evaluations before proceed towards the final ASIC product. The overall platform is composed by hardware blocks and software tools suitable for the design space exploration, while a proper verification methodology is being adopted to guarantee the correct system behaviour. In order to tune the platform architecture with an application case and at the same time to demonstrate its flexibility, two case examples are being examined