Memory Access Optimization of a Neural Network Accelerator Based on Memory Controller

Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access performance is relatively poor, limiting the overall performance improvement of hardware accelerators. Moreover, memory controllers for hardware accelerators have been scarcely researched. We consider that a special accelerator memory controller is essential for improving the memory access performance. To this end, we propose a dynamic random access memory (DRAM) memory controller called NNAMC for neural network accelerators, which monitors the memory access stream of an accelerator and transfers it to the optimal address mapping scheme bank based on the memory access characteristics. NNAMC includes a stream access prediction unit (SAPU) that analyzes the type of data stream accessed by the accelerator via hardware, and designs the address mapping for different banks using a bank partitioning model (BPM). The image mapping method and hardware architecture were analyzed in a practical neural network accelerator. In the experiment, NNAMC achieved significantly lower access latency of the hardware accelerator than the competing address mapping schemes, increased the row buffer hit ratio by 13.68% on average (up to 26.17%), reduced the system access latency by 26.3% on average (up to 37.68%), and lowered the hardware cost. In addition, we also confirmed that NNAMC efficiently adapted to different network parameters

A Low Power Energy-Efficient Precision CMOS Temperature Sensor †

This paper presents a low power, energy-efficient precision CMOS temperature sensor. The front-end circuit is based on bipolar junction transistors, and employs a pre-bias circuit and bipolar core. To reduce measurement errors arising from current ratio mismatch, a new dynamic element-matching mode is proposed, which dynamically matches all current sources in the front-end circuit. The first-order fitting and third-order fitting are used to calibrate the output results. On the basis of simulation results, the sensor achieves 3σ-inaccuracies of +0.18/−0.13 °C from −55 °C to +125 °C. Measurement results demonstrate sensor 3σ-inaccuracies of ±0.2 °C from 0 °C to +100 °C. The circuit is implemented in 0.18 μm CMOS, and consumes 6.1 μA with a 1.8 V supply voltage

Analysis of Orthogonal Coupling Structure Based on Double Three-Contact Vertical Hall Device

A vertical Hall device is an important component of 3D Hall sensors, used for detecting magnetic fields parallel to the sensor surface. The Hall devices described in existing research still have problems, such as large offset voltage and low sensitivity. Aiming to solve these problems, this study proposes a double three-contact vertical Hall device with low offset voltage, and a conformal mapping analysis method to improve the sensitivity of the device. Secondly, an orthogonal coupling structure composed of two sets of double three-contact vertical Hall devices is proposed, which further reduces the offset voltage of the device. Finally, the TCAD simulation software was used to analyze the performance of the devices, and an existing vertical Hall device was compared to ours. The results show that the orthogonal coupling structure in this study exhibits better performance, reaching an average voltage sensitivity of 17.5222 mV/VT and an average offset voltage of about 0.075 mV. In addition, the structure has the same magnitude of offset voltage in the four phases of the rotating current method. This characteristic enables the back-end circuit to more accurately filter out the offset voltage and acquire the Hall signal

Algorithm of global escape routing problem based on linear programming

As a key part of PCB design, the ordered escape routing problem is a special NP-hard problem, which has been studied extensively in recent years. In the traditional method, both ILP method and the heuristic algorithms based on ripping-up and rerouting are only applicable to small-scaled pin arrays with fewer pins, which easily lead to time violation. Aiming at the difficulty of large-scale global routing in traditional methods, the iteration-driven method is proposed to solve the global escaping routing problem by linear programming (LP), and to optimize area congestion by reducing capacity. Compared with the latest work, this algorithm can not only escape all pins but also achieve up to 50% times speed up and save 31% wire length

High-Fidelity and High-Efficiency Digital Class-D Audio Power Amplifier

This study presents a high-fidelity and high-efficiency digital class-D audio power amplifier (CDA), which consists of digital and analog modules. To realize a compatible digital input, a fully digital audio digital-to-analog converter (DAC) is implemented on MATLAB and Xilinx System Generator, which consists of a 16x interpolation filter, a fourth-order four-bit quantized delta-sigma (ΔΣ) modulator, and a uniform-sampling pulse width modulator. The CDA utilizes the closed-loop negative feedback and loop-filtering technologies to minimize distortion. The audio DAC, which is based on a field-programmable gate array, consumes 0.128 W and uses 7100 LUTs, which achieves 11.2% of the resource utilization rate. The analog module is fabricated in a 0.18 µm BCD technology. The postlayout simulation results show that the CDA delivers an output power of 1 W with 93.3% efficiency to a 4 Ω speaker and achieves 0.0138% of the total harmonic distortion (THD) with a transient noise for a 1 kHz input sinusoidal test tone and 3.6 V supply. The output power reaches up to 2.73 W for 1% THD (with transient noise). The proposed amplifier occupies an active area of 1 mm2

Low-Power CMOS Integrated Hall Switch Sensor

This paper presents an integrated Hall switch sensor based on SMIC 0.18 µm CMOS technology. The system includes a front-end Hall element and a back-end signal processing circuit. By optimizing the structure of the Hall element and using the orthogonal coupling and spinning current technology, the offset voltage can be suppressed effectively. The simulation results showed that the Hall switch can eliminate offset voltage greater than 1 mV at 3.3 V supply voltage. Two modes of the Hall switch circuit, the awake mode and the sleep mode, were realized by using clock logic signals without compromising the performance of the Hall switch, thereby reducing power consumption. The test results showed that the operate point and the release point of the switch were within the range of 3–7 mT at 3.3 V supply voltage. Meanwhile, the current consumption is 7.89 µA